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  doc. no. 100723a june 21, 2000 MFC2000 multifunctional peripheral controller 2000 hardware description
ii conexant 100723a ordering information marketing name device set order no. part no. package part no. package MFC2000 xxx-xxx-xxx xxxxx revision history revision date comments a 04/07/00 initial, internal, preliminary release of document. a 06/21/00 second internal, preliminary release with revisions tracked. ? 2000, conexant systems, inc. all rights reserved. information in this document is provided in connection with conexant systems, inc. ("conexant") products. these materials are p rovided by conexant as a service to its customers and may be used for informational purposes only. conexant assumes no responsibility for errors or omissions in these materials. conexant may make changes to specifications and product descriptions at any time, without notice. conexant makes no commitment to update the information contained herein. conexant shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. exce pt as provided in conexant?s terms and conditions of sale for such products, conexant assumes no liability whatsoever. these materials are provided "as is" without warranty of any kind, either express or implied, relating to sale and/or use of conexant products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. conexant further does not warrant the accuracy or completeness of the information, text, graphics or other item s contained within these materials. conexant shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. conexant products are not intended for use in medical, life saving or life sustaining applications. conexant customers using or selling conexant products for use in such applications do so at their own risk and agree to fully indemnify conexant for any damages re sulting from such improper use or sale. the following are trademarks of conexant systems, inc.: conexant, the conexant c symbol, ?what?s next in communications technol ogies?, and smartdaa. product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. third-party brands and names are the property of their respective owners. reader response: conexant strives to produce quality documentation and welcomes your feedback. please send comments and suggestions to conexant.tech.pubs@conexant.com. for technical questions, contact your local conexant sales office or field applications engineer.
100723a conexant iii contents 1. introduction ................................................................................................................. ............................. 1-1 1.1 scope ....................................................................................................................... ............................... 1-1 1.2 system overview ............................................................................................................. ................... 1-1 1.3 reference documentation..................................................................................................... ....... 1-5 2. MFC2000 summary .............................................................................................................. ........................ 2-1 2.1 MFC2000 device family....................................................................................................... ................ 2-1 2.2 MFC2000 system block diagram ................................................................................................ .... 2-1 3. hardware interface........................................................................................................... .................... 3-1 3.1 pin description ............................................................................................................. ...................... 3-1 3.2 maximum ratings............................................................................................................. .................... 3-7 3.3 electrical characteristics.................................................................................................. ........ 3-8 3.4 pin layout.................................................................................................................. .......................... 3-10 4. cpu and bus interface ........................................................................................................ ................... 4-1 4.1 memory map and chip select description ............................................................................... 4-1 4.2 cache memory controller..................................................................................................... ..... 4-19 4.3 siu???. ..................................................................................................................... .......................... 4-24 4.4 interrupt controller........................................................................................................ ........... 4-46 4.5 dram controller (including battery dram) ........................................................................ 4-54 4.6 flash memory controller..................................................................................................... ...... 4-72 4.7 dma controller .............................................................................................................. ................. 4-76 5. reset logic/battery backup/watch dog timer........................................................................... 5-1 5.1 reset logic/battery backup .................................................................................................. ....... 5-1 5.2 watchdog timer .............................................................................................................. ................. 5-11 6. fax timing control interface ................................................................................................. ........... 6-1 6.1 pll????.. ................................................................................................................... ......................... 6-1 6.2 fax timing logic ............................................................................................................ ...................... 6-2 6.3 MFC2000 timing chain ........................................................................................................ ................. 6-3 6.4 scan control timing......................................................................................................... ................ 6-4 6.5 fax timing registers........................................................................................................ ................. 6-5 7. video/scanner controller ..................................................................................................... ............ 7-1 7.1 scanner controller.......................................................................................................... .............. 7-2 7.2 serial programming interface................................................................................................ .. 7-41 7.3 video controller ............................................................................................................ ................ 7-50 8. adc??........................................................................................................................ ................................... 8-1 8.1 padc and scan analog front end .............................................................................................. .8-1 8.2 tadc????????. ............................................................................................................... ............ 8-5
iv conexant 100723a 9. bi-level resolution conversion ............................................................................................... ........ 9-1 9.1 functional description ...................................................................................................... ............ 9-1 9.2 register description ........................................................................................................ ............... 9-6 9.3 resolution conversion programming examples............................................................... 9-15 10. external print asic interface ............................................................................................... .......... 10-1 10.1 interface between the MFC2000 and external print asic .......................................... 10-1 11. bit rotation logic.......................................................................................................... ........................ 11-1 11.1 functional description ..................................................................................................... ....... 11-1 11.2 block diagram.............................................................................................................. ................. 11-3 11.3 register description....................................................................................................... .......... 11-6 11.4 firmware operation......................................................................................................... ........ 11-10 12. printer and scanner stepper motor interface ...................................................................... 12-1 12.1 vertical print stepper motor interface ......................................................................... 12-1 12.2 scanner stepper motor interface ..................................................................................... 12-5 13. general purpose inputs/outputs (gpio) ...................................................................................... 1 3-1 13.1 gpio signals ............................................................................................................... .................... 13-1 13.2 gpo/gpi signals............................................................................................................ ................. 13-5 13.3 gpio control and data registers........................................................................................ 13-6 14. compressor and decompressor................................................................................................. .... 14-1 14.1 functional description ..................................................................................................... ....... 14-1 14.2 register description....................................................................................................... .......... 14-2 15. synchronous/asynchronous serial interface (sasif) ......................................................... 15-1 15.1 functional description ..................................................................................................... ....... 15-1 15.2 register description....................................................................................................... .......... 15-3 15.3 sasif timing............................................................................................................... .................... 15-12 15.4 firmware operation......................................................................................................... ........ 15-16 16. usb interface ............................................................................................................... ........................... 16-1 16.1 function description ....................................................................................................... ......... 16-1 16.2 register description....................................................................................................... .......... 16-1 16.3 firmware operation......................................................................................................... ........ 16-23 17. bi-directional parallel peripheral interface........................................................................ 17-1 17.1 operational modes.......................................................................................................... ........... 17-1 17.2 additional features........................................................................................................ ........... 17-2 17.3 functional description ..................................................................................................... ....... 17-3 17.4 register description....................................................................................................... .......... 17-4 17.5 timing ..................................................................................................................... ......................... 17-16 17.6 firmware operation......................................................................................................... ........ 17-22
100723a conexant v 18. real-time clock ............................................................................................................. ......................... 18-1 18.1 description ................................................................................................................ .................... 18-1 18.2 real-time clock (rtc) registers ........................................................................................... 1 8-2 18.3 rtc operations............................................................................................................. ................ 18-3 19. synchronous serial interface (ssif)......................................................................................... ... 19-1 19.1 introduction and features .................................................................................................. .. 19-1 19.2 register description....................................................................................................... .......... 19-2 19.3 ssif timing ................................................................................................................ ....................... 19-7 20. programmable tone generators ................................................................................................ .. 20-1 20.1 introduction ............................................................................................................... .................. 20-1 20.2 bell/ringer generator ...................................................................................................... ....... 20-1 20.3 tone generator............................................................................................................. .............. 20-6 21. pwm logic ................................................................................................................... ............................... 21-1 21.1 functional description ..................................................................................................... ....... 21-1 21.2 register description....................................................................................................... .......... 21-2 22. calling party control (cpc) ................................................................................................. ........... 22-1 22.1 registers description ...................................................................................................... ........ 22-5 23. ssd_p80 ..................................................................................................................... ................................... 23-1 23.1 function description ....................................................................................................... ......... 23-1 23.2 register description....................................................................................................... .......... 23-3 23.3 firmware operation......................................................................................................... .......... 23-6 24. countach imaging dsp bus subsystem ......................................................................................... 2 4-1 24.1 countach imaging dsp subsystem........................................................................................ 24-3 24.2 countach imaging dsp bus unit ............................................................................................. 2 4-4 24.3 arm bus interface.......................................................................................................... ............. 24-8 24.4 countach imaging dsp subsystem interface ................................................................ 24-11 24.5 countach dma controller.................................................................................................... 24-12 24.6 video/scanner interface .................................................................................................... ... 24-22 24.7 (s)dram controller ((s)dramc) ............................................................................................ 24 -23 24.8 register description....................................................................................................... ........ 24-28 25. configuration ............................................................................................................... .......................... 25-1 25.1 hardware version ........................................................................................................... ........... 25-1 25.2 product code ............................................................................................................... ................ 25-1
vi conexant 100723a figures figure 1-1. mfp system diagram using MFC2000 ................................................................................... ........................... 1-1 figure 1-2: MFC2000 function diagram ........................................................................................... .................................... 1-4 figure 2-1. MFC2000 organization ............................................................................................................................... ........ 2-2 figure 3-1. MFC2000 bga bottom view ............................................................................................ ................................. 3-10 figure 4-1. MFC2000 memory map................................................................................................. ...................................... 4-6 figure 4-2. MFC2000 internal memory map........................................................................................ .................................. 4-7 figure 4-3. MFC2000 cache organization ......................................................................................... ................................. 4-19 figure 4-4. 2-way interleave rom connection.................................................................................... ............................... 4-26 figure 4-5. zero wait state, single access, normal read, normal write .......................................................... ................. 4-36 figure 4-6. one wait state, single access, one read, one write ................................................................. .................... 4-37 figure 4-7. two wait states, single access, read on delayed (cs1n), write early off (cs2n)..................................... ... 4-38 figure 4-8. zero wait state, burst access, normal read, normal write........................................................... .................. 4-39 figure 4-9. fast page mode rom access ? 1,0,0 read access followed by 1,1,1,1, write access.................................. 4-40 figure 4-10. system bus timing ? read/write with wait states ......................................................................................... 4-41 figure 4-11. system bus timing ? zero-wait-state read/write.......................................................................................... 4-42 figure 4-12. system bus timing ? 2-way interleave read timing (s = 1).......................................................................... 4-43 figure 4-13. system bus timing ? 2-way interleave write timing (s = 0 or 1)................................................................... 4-44 figure 4-14. external interrupt request timing................................................................................. .................................. 4-54 figure 4-15. dram bank/address map............................................................................................. .................................. 4-56 figure 4-16. simplified dram controller block diagram .......................................................................... .......................... 4-59 figure 4-17. dram interface example ............................................................................................ .................................... 4-60 figure 4-18. 8-bit memory data bus............................................................................................. ....................................... 4-65 figure 4-19. 16-bit memory data bus............................................................................................ ...................................... 4-65 figure 4-20. casn non-interleaved 8-bit dram read.............................................................................. .......................... 4-66 figure 4-21. 2-way interleaved memory with halfword bursts of data ............................................................. .................. 4-66 figure 4-22. 2-way interleaved dram read (3 words) ............................................................................. ......................... 4-67 figure 4-23. 2-way interleaved dram write ...................................................................................... ................................ 4-67 figure 4-24. refresh cycle..................................................................................................... ............................................. 4-68 figure 4-25. dram timing ? read, write and wait states for non-interleave mode .......................................................... 4-68 figure 4-26. dram timing for 2-way interleave write ............................................................................ ............................ 4-69 figure 4-27. dram timing ? read for 2-way interleave mode............................................................................................ 4-69 figure 4-28. dram refresh timing ............................................................................................... ..................................... 4-70 figure 4-29. dram battery refresh timing ....................................................................................... ................................. 4-70 figure 4-30. flash control block diagram....................................................................................... .................................... 4-73 figure 4-31. nand-type flash memory access with two wait states ................................................................ .............. 4-75 figure 4-32: external dma read timing (single access, one wait state) ....................................................................... .. 4-80 figure 4-33. external dma write timing (single access, one wait state) ......................................................... ................ 4-81 figure 4-34. usb logical channels block diagram ................................................................................ ............................ 4-82 figure 5-1. power reset block diagram.......................................................................................... ...................................... 5-2
100723a conexant vii figure 5-2. power-down select logic............................................................................................ ........................................ 5-3 figure 5-3. power reset timing diagram......................................................................................... ..................................... 5-5 figure 5-4. +5v prime power signal and vgg ..................................................................................... ................................. 5-6 figure 5-5. internal power detection ........................................................................................... ........................................ 5-10 figure 5-6. figure caption required ............................................................................................ ....................................... 5-10 figure 5-7. voltage divider circuit............................................................................................ ........................................... 5-11 figure 5-8. watchdog timer block diagram....................................................................................... ................................. 5-12 figure 5-9. watchdog time-out timing diagram ................................................................................... ............................. 5-13 figure 6-1. fax timing control logic block diagram ............................................................................. ............................... 6-2 figure 6-2. MFC2000 timing chain ............................................................................................... ....................................... 6-3 figure 6-3. scan control timing................................................................................................ ............................................ 6-4 figure 7-1. video/scanner controller block diagram ............................................................................. ............................... 7-1 figure 7-2. untitled timing diagram............................................................................................ ........................................ 7-19 figure 7-3. untitled timing diagram............................................................................................ ........................................ 7-20 figure 7-4. untitled timing diagram............................................................................................ ........................................ 7-20 figure 7-5. untitled timing diagram............................................................................................ ........................................ 7-21 figure 7-6. untitled timing diagram............................................................................................ ........................................ 7-22 figure 7-7. untitled timing diagram............................................................................................ ........................................ 7-23 figure 7-8. untitled timing diagram............................................................................................ ........................................ 7-23 figure 7-9. untitled timing diagram............................................................................................ ........................................ 7-24 figure 7-10. untitled timing diagram........................................................................................... ....................................... 7-24 figure 7-11. untitled timing diagram........................................................................................... ....................................... 7-24 figure 7-12. untitled timing diagram........................................................................................... ....................................... 7-25 figure 7-13. untitled timing diagram........................................................................................... ....................................... 7-25 figure 7-14. untitled timing diagram........................................................................................... ....................................... 7-26 figure 7-15. untitled timing diagram........................................................................................... ....................................... 7-28 figure 7-16. untitled timing diagram........................................................................................... ....................................... 7-30 figure 7-17. untitled timing diagram........................................................................................... ....................................... 7-32 figure 7-18. untitled timing diagram........................................................................................... ....................................... 7-34 figure 7-19. untitled timing diagram........................................................................................... ....................................... 7-36 figure 7-20. untitled timing diagram........................................................................................... ....................................... 7-38 figure 7-21. external circuit required for sony?ilx516k interface .............................................................. ...................... 7-40 figure 7-22. led timing for sony?ilx516k....................................................................................... ................................ 7-40 figure 7-23. serial programming interface, physical connection ................................................................. ...................... 7-41 figure 7-24. bus protocol ...................................................................................................... .............................................. 7-42 figure 7-25. serial programming interface, timing diagram...................................................................... ......................... 7-42 figure 7-26. stretching the low period of the clock ............................................................................ ............................... 7-44 figure 7-27. firmware operation ? transmission................................................................................................................ 7-4 8 figure 7-28. firmware operation ? reception ..................................................................................................................... 7 -49 figure 7-29. connection to external video capture device ....................................................................... ......................... 7-51 figure 7-30. untitled timing diagram........................................................................................... ....................................... 7-54
viii conexant 100723a figure 7-31. dma operation..................................................................................................... ........................................... 7-55 figure 8-1. untitled figure .................................................................................................... ................................................. 8-1 figure 9-1: bi-level resolution conversion block diagram ....................................................................... ............................ 9-2 figure 9-2. the physical nozzle diagram for typical inkjet heads ............................................................... ........................ 9-5 figure 9-3. untitled figure .................................................................................................... ................................................. 9-5 figure 9-4: resolution conversion programming.................................................................................. .............................. 9-15 figure 10-1. print asic interface.............................................................................................. ........................................... 10-2 figure 11-1. nozzle diagram of a typical programmable inkjet head .............................................................. .................. 11-1 figure 11-2. examples of nozzle head configurations ............................................................................ ........................... 11-2 figure 11-3. nozzle configuration by bit rotation block (regardless of physical nozzle configuration) .......................... . 11-2 figure 11-4. MFC2000 bit rotation block diagram................................................................................ ............................. 11-3 figure 11-5. fetcher dma channel fetch order................................................................................... .............................. 11-4 figure 11-6. cpu background print data preparation ............................................................................. ......................... 11-12 figure 11-7. MFC2000 little-endian format ...................................................................................... ............................... 11-13 figure 12-1. vertical printer motor control block diagram ...................................................................... ............................ 12-1 figure 12-2. stepping timing ................................................................................................... ........................................... 12-2 figure 12-3. scan motor control diagram ........................................................................................ ................................... 12-5 figure 12-4. stepping timing ................................................................................................... ........................................... 12-7 figure 12-5: current control diagram ........................................................................................... ...................................... 12-9 figure 14-1. data flow for compression/decompression ........................................................................... ........................ 14-1 figure 14-2. compressor/decompressor fifo structure ............................................................................ ........................ 14-2 figure 15-1. sasif block diagram............................................................................................... ....................................... 15-2 figure 15-2. sassclk timing diagram............................................................................................ ................................ 15-12 figure 15-3. synchronous mode timing........................................................................................... ................................. 15-13 figure 15-4. asynchronous transmitter timing................................................................................... .............................. 15-14 figure 17-1. parallel port interface controller block diagram .................................................................. ........................... 17-3 figure 17-2. compatibility mode timing diagram................................................................................. ............................. 17-16 figure 17-3. nibble mode data transfer cycle ................................................................................... .............................. 17-17 figure 17-4. byte mode data transfer cycle ..................................................................................... ............................. 17-18 figure 17-5. ecp mode timing diagram........................................................................................... ................................ 17-19 figure 17-6. reverse ecp transfer timing....................................................................................... ................................ 17-20 figure 17-7. error cycle timing diagram ........................................................................................ .................................. 17-21 figure 18-1. rtc block diagram................................................................................................. ........................................ 18-1 figure 19-1. ssif block diagram ................................................................................................ ........................................ 19-1 figure 19-2. ssclk1 diagram .................................................................................................... ........................................ 19-3 figure 19-3. ssclk2 diagram .................................................................................................... ........................................ 19-6 figure 19-4. timing diagram .................................................................................................... ........................................... 19-8 figure 20-1. bell/ringer timing ................................................................................................ ........................................... 20-1 figure 20-2. bell/ringer block diagram ......................................................................................... ..................................... 20-2 figure 20-3. bell/ringer generator waveform .................................................................................... ................................ 20-3 figure 20-4. tone generator frequency change................................................................................... ............................. 20-6
100723a conexant ix figure 22-1: cpc signal........................................................................................................ .............................................. 22-1 figure 22-2. cpc operation flowchart ........................................................................................... .................................... 22-2 figure 22-3: cpc operation (with cpcthreshold = 4)............................................................................. ........................... 22-3 figure 22-4: cpc block diagram ................................................................................................. ....................................... 22-4 figure 23-1. system configuration one .......................................................................................... .................................... 23-1 figure 23-2. system configuration two .......................................................................................... .................................... 23-2 figure 23-3. system configuration three........................................................................................ .................................... 23-2 figure 24-1. the arm bus system block diagram.................................................................................. ........................... 24-2 figure 24-2. sdram setup and hold timing ....................................................................................... ............................. 24-29 figure 24-3. sdram read or write timing........................................................................................ ............................... 24-30 figure 24-4. sdram mode timing................................................................................................. ................................... 24-30 figure 24-5. sdram refresh timing .............................................................................................. .................................. 24-30 figure 24-6. fpdram timing (read or write) ..................................................................................... ............................. 24-31 figure 24-7. fpdram timing (refresh)........................................................................................... ................................. 24-33
x conexant 100723a tables table 1-1. reference documentation............................................................................................. ....................................... 1-5 table 2-1. MFC2000 device family ............................................................................................... ....................................... 2-1 table 3-1. pin description (1 of 6) ............................................................................................ ............................................. 3-1 table 3-2. maximum ratings..................................................................................................... ............................................ 3-7 table 3-3. digital input characteristics ....................................................................................... ........................................... 3-8 table 3-4. output characteristics .............................................................................................. ............................................ 3-8 table 3-5. power supply requirements ........................................................................................... ..................................... 3-9 table 3-6. battery power supply current requirements........................................................................... ............................ 3-9 table 4-1. fixed-location and size chip selects ................................................................................ .................................. 4-4 table 4-2. operation register map (1 of 9) ..................................................................................... ...................................... 4-8 table 4-3. setup registers (1 of 2)............................................................................................ .......................................... 4-17 table 4-4. cache tag data format (for test mode read/write operation) .......................................................... .............. 4-20 table 4-5. access modes for reading rom ........................................................................................ ............................... 4-27 table 4-6. read operation (internal peripheral gets data from memory) .......................................................... ............... 4-29 table 4-7. write operation (internal peripheral puts data into memory) ......................................................... ................... 4-29 table 4-8. read/write with wait states timing parameters....................................................................... ......................... 4-45 table 4-9. MFC2000 interrupt and reset signals ................................................................................. .............................. 4-46 table 4-10. programmable resolution of timer1 and timer2 ....................................................................... ...................... 4-53 table 4-11. dram wait state configurations ..................................................................................... ................................ 4-55 table 4-12. address multiplexing ? part 1 ......................................................................................................................... .. 4-57 table 4-13. address multiplexing ? part 2 ......................................................................................................................... .. 4-57 table 4-14. dram row/column configuration ...................................................................................... ............................. 4-58 table 4-15. dram timing parameters............................................................................................. ................................... 4-71 table 4-16. feature matrix ..................................................................................................... ............................................. 4-77 table 4-17. dma channel functions and characteristics .......................................................................... ......................... 4-78 table 4-18 dma channel 3 control bit sssignment................................................................................ ............................ 4-79 table 6-1. operation mode frequencies .......................................................................................... ..................................... 6-1 table 7-1. register setup for rohm?ia3008?ze22................................................................................. ............................ 7-27 table 7-2. register setup for dyna?dl507?07uah................................................................................. ........................... 7-29 table 7-3. register setup for mitsubishi-gt3r216............................................................................... ............................... 7-31 table 7-4. register setup for toshiba?cips218mc300 ............................................................................. ........................ 7-33 table 7-5. register setup for nec ? pd3724 ................................................................................................................... 7-35 table 7-6. register setup for nec ? pd3794.................................................................................................................... 7-37 table 7-7. register setup for sony ? ilx516k................................................................................... ............................... 7-39 table 8-1. untitled table ...................................................................................................... ................................................. 8-2 table 8-2. untitled table ...................................................................................................... ................................................. 8-2 table 8-3. offset adjustment on dac ............................................................................................ ....................................... 8-2 table 8-4. programmable gain amplifier (pga)................................................................................... ................................. 8-3 table 8-5. pipelined adc (padc)................................................................................................ ......................................... 8-4
100723a conexant xi table 8-6. padc timing diagram ................................................................................................. ........................................ 8-4 table 8-7. tadc block diagram .................................................................................................. ......................................... 8-5 table 9-1. untitled table ...................................................................................................... ................................................. 9-2 table 9-2: procedure to determine pixels to remove............................................................................. .............................. 9-17 table 9-3: resolution conversion examples...................................................................................... ................................. 9-17 table 12-1. full step/single phase excitation.................................................................................. ................................... 12-3 table 12-2. full step/two phase excitation ..................................................................................... ................................... 12-3 table 12-3. half-step excitation ............................................................................................... ........................................... 12-3 table 12-4. full step/single phase excitation.................................................................................. ................................... 12-7 table 12-5. full step/two phase excitation ..................................................................................... ................................... 12-7 table 12-6. half-step excitation ............................................................................................... ........................................... 12-8 table 18-1. rtc crystal specifications for 32.768 khz.......................................................................... ............................. 18-4 table 20-1. bell/ringer setting................................................................................................ ............................................ 20-2 table 23-1. ssd registers ...................................................................................................... ............................................ 23-4 table 23-2. p80 core registers................................................................................................. ....................................... 23-5 table 24-1. needs a title...................................................................................................... .............................................. 24-11 table 24-2. dma channels: functionality and priorities ......................................................................... .......................... 24-12 table 24-3. dma parameters scratch pad addresses............................................................................... ....................... 24-13 table 24-4: supported fpdram chip characteristics.............................................................................. ........................ 24-23 table 24-5: supported sdram chip characteristics ............................................................................... ......................... 24-23 table 24-6. untitled table..................................................................................................... .............................................. 24-25 table 24-7. untitled table..................................................................................................... .............................................. 24-26 table 24-8. untitled table..................................................................................................... .............................................. 24-26 table 24-9. sdram setup and hold timing ........................................................................................ ............................. 24-29 table 24-10. timing parameters for 16-bit sdram read and write ................................................................. ............... 24-31 table 24-11. timing parameters for 8-bit sdram read and write .................................................................. ................ 24-31 table 24-12. 60ns timing ....................................................................................................... ........................................... 24-32 table 24-13. 50ns timing ....................................................................................................... ........................................... 24-32 table 24-14. fpdram timing (refresh)........................................................................................... ................................ 24-33
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hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 1-1 1. introduction 1.1 scope this document defines and describes all hardware functions of the MFC2000 chip. the MFC2000 design is based on the mfc1000 design with many minor modifications/enhancements. it has several new key functions to accomplish the following: ? support a full color mfp ? enhance connectivity to the pc ? provide an internal fax modem ? connect to external conexant video chips 1.2 system overview the conexant multi-functional peripheral controller 2000 (MFC2000) device set hardware, core code, application code, and evaluation system comprise a full color multi-functional peripheral (mfp) system ? needing only a power supply, scanner, printer mechanism, and paper path components to complete the machine. the standard device set hardware includes conexant?s MFC2000 chip, conexant?s smartdaa or ia chip, and a printer interface chip. optionally, a conexant video chip with vip interface can be used to support the video capture function. if v.17 or v.34 faxing without voice is required, the internal v.17/v.34 fax modem in the MFC2000 chip is used and the MFC2000 is connected to the external conexant smartdaa or ia chip. if the voice/speech function is required, the external voice fax modem device from conexant will be needed. any other external interface device can be supported by using the external arm for cpu and dma accesses or by using the internal serial interface. an mfp system-level block diagram using the mfc 2000 is illustrated in figure 1-1. MFC2000 (conexant) operator panel module pc serial interface (sync.) printer if (conexant) color inkjet printer scanner interface color scanner module program rom/flash memory data dram/sram/flash memory spi and vip interface usb interface or p1284 interface prime power/ battery power hybrid and power down circuit vdd battery video chip (conexant) video camera ntsc /pal smartdaa (conexant) conexant proprietary interface telephone line (color faxing) video/scan sdram/dram external arm bus figure 1-1. mfp system diagram using MFC2000
MFC2000 multifunctional peripheral controller 2000 hardware description 1-2 conexant 100723a 1.2.1 integrated full color mfp controller (MFC2000) the MFC2000 provides the majority of the electronics necessary to build a color scan and color inkjet printer based mfp whose electronics are integrated into a one-chip solution including one cpu (arm7tdmi) and two dsps (countach imaging dsp subsystem and p80 core). full printer and copier functionality is provided by the following: ? 1284 parallel port interface ? usb serial port interface ? color scanner interface/controller ? countach imaging dsp subsystem for video/scan/compression process ? flash memory controller ? sdram/dram controllers ? resolution conversion logic ? inkjet data formatter ? external inkjet printing in addition, the MFC2000 performs facsimile control/monitoring, compression/decompression, and 33.6 kbps fax modem functions (p80 core). the MFC2000 interfaces with major mfp machine components like external modems, smartdaa, external fax ia, motors, sensors, external video chip, and operator control panel. the arm7tdmi-embedded processor provides an external 48-mb direct memory access capability. an integrated 12-bit pipeline adc (padc) and countach subsystem (dsp subsystem, combined with an advanced conexant proprietary color image processing algorithm, provides state of the art image processing performance on any type of images, including text/half-tone and color images. the full color mfp engine provides the hardware and software necessary to develop a full-color multifunctional peripheral including an architecture for color printing, color faxing, color scanning, video capturing, and color copying. it also supports many of these operations concurrently. 1.2.1.1 printing the MFC2000 controller supports color inkjet printing. print speed throughput capabilities are inversely proportional to resolution and also depend on the external printer interface. for host printing, the host sends the image data with the print resolution; the MFC2000 performs no resolution conversion. if host printing and faxing need to be performed for the same image, the printing image data must be sent to the mfp. the MFC2000 converts the printing image data to the faxing image data locally and then faxes it out. an external printer interface chip is designed to support inkjet print mechanism/head subsystems. different external printer interface chips can be designed and used to support other inkjet mechanisms and heads according to customer requirements. 1.2.1.2 faxing both host-based color faxing and standalone color faxing are supported in addition to monochrome faxing. host- based faxing can take place by using a class one connection via the usb serial port or the p1284 parallel port. for host faxing, the host sends the image data with the fax resolution; the MFC2000 performs no resolution conversion. for standalone faxing, the resolution conversion is supported by the MFC2000. the standalone color scan-to-fax function is supported using the advanced conexant proprietary color image processing technology: ? shading correction ? gamma correction ? pixel-based dark-level correction ? color/monochrome image processing ? color conversion ? jpeg ? multi-level resolution conversion.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 1-3 1.2.1.3 scanning for the color scan-to-pc function, up to 8 bits of scan data per pixel can be sent to the host. jpeg compression can be used to reduce the pc upload speed. 1.2.1.4 copying the MFC2000 and associated firmware supports several modes of copying including standard, fine, superfine, and photo. multiple copies of a single image can be made with a single pass. the standalone color/monochrome copy function is supported by using MFC2000?s inkjet print formatter, the external printer interface, and the advanced conexant proprietary color image processing system. 1.2.2 MFC2000 evaluation system the conexant MFC2000 evaluation system provides demonstration, prototype development, and evaluation capabilities to full color mfp developers using the MFC2000 engine device set. the MFC2000 evaluation system provides flexibility for visibility and access, i.e., plug-on board for the modem, sockets for programmable parts, and connectors for an emulator (refer to figure 1-2). jumper options and test points are provided throughout the MFC2000 evaluation main board. the MFC2000 evaluation system is the most convenient environment for the developer needing to experiment with the several interfaces encountered in the full color mfp, for example, color printer functions. 1.2.3 new function highlights ? pll clock generation for several different clocks needed for arm cpu, countach imaging dsp, fax modem core, and usb interface ? 4 kb 2-way set associative instruction cache ? usb interface (including usb transceiver) to pc ? video/ color scan controller (up to 600 dpi) (including programmable adc sampling rate) ? countach imaging dsp subsystem for pixel-based dark level correction, shading correction, gamma correction, video/color scan image processing, color science and jpeg ? countach bus system which includes countach subsystem interface, arm bus interface, video/scan interface, countach bus unit, countach dma controller, and sdram controller. ? smartdaa/ia interface ? p80 core + arm ipb interface logic (v.34 fax modem core) ? two sync. serial interfaces ? color scan ia which includes color scan analog front end, 12-bit padc, power-down voltage detection circuit, and tadc reference voltage. ? spi and vip interface to the external conexant video chip
MFC2000 multifunctional peripheral controller 2000 hardware description 1-4 conexant 100723a MFC2000 countach bus system video/scan controller countach subsystem (for video/scan image processing) internal peripheral bus siu external arm bus external system memory mono and color cis/ ccd control scanner in 16 ntsc/ pal signal arm7tdmi cache controller and memory (4kb) dma controller all logic blocks on the internal system bus from mfc1000 external local (s)dram 2 dma channels for the arm bus system 12-bit padc analog frontend pll 30 mhz, 37.5 mhz, or 40 mhz 100 mhz or 85.7 mhz usb if 16 32 32 cdmac sdramc 28.224 mhz 16 or 8 external conexant video chip spi vip video /scan if countach subsystem if arm bus if countach bus unit 28.224 mhz for modem p1284 if p80 core smart daa if arm ipb if 48 mhz for usb figure 1-2: MFC2000 function diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 1-5 1.3 reference documentation table 1-1. reference documentation document number MFC2000 data sheet 100505 MFC2000 firmware architecture 100972 MFC2000 hardware description (this document) 100723 MFC2000 programmer?s reference manual 100971
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multifunctional peripheral controller 2000 MFC2000 100723a conexant 2-1 2. MFC2000 summary 2.1 MFC2000 device family the MFC2000 contains an internal 32-bit risc processor with 64-mb address space, the countach imaging dsp (conexant?s dsp) subsystem including embedded data and program memory, and dedicated circuitry optimized for color scanning, color faxing, color copying, color printing, and multifunctional control and monitoring. the device family with relevant features is described in table 2-1. table 2-1. MFC2000 device family device no. product code data modem function voice codec/speaker phone functions smart daa support cx0720x-11 bfh yes yes yes cx0720x-12 bdh yes no yes cx0720x -13 bbh no yes yes cx0720x -14 b9h no no yes cx0720x-15 b8h no no no 2.2 MFC2000 system block diagram the MFC2000 contains the arm7tdmi risc processor (described separately in arm7tdmi manuals), countach imaging dsp, modem dsp, and specialized hardware needed for the multifunctional machine control and scanner and fax signal processing. the countach imaging dsp subsystem is on a separate data bus. therefore, the arm system data bus can operate in parallel with the countach imaging dsp subsystem data bus for most operations except the interaction time between two buses. the two-bus architecture is very important to provide enough bandwidth for full color mfp products. figure 2-1 shows the mfp2000?s two-bus architecture. the arm bus system (abs) has two masters ? arm cpu and dma controller. they provide accesses to all specialized hardware functions including the countach imaging dsp subsystem as a peripheral on the arm bus system. abs has several sections. the system interface unit (siu) is the control center. the arm cpu and cache controller are on the internal system bus (isb). the cache memory is on the internal cache bus (icb). the dma controller is on the dma bus (dab). all internal peripherals are on the internal peripheral bus (ipb). the smartdaa/ia interface and p80 core are on the ipb of the arm bus system. the arm7tdmi runs at a clock rate 40 mhz, 37.5 mhz, or 30 mhz. all external peripherals are on the arm external bus (aeb). there is a separate bus system for the countach imaging dsp subsystem called countach bus system (cbs). there are three sections, the video/scan interface, the arm bus interface, and the countach subsystem interface. the external sdram/dram is on the countach external bus (ceb).
MFC2000 multifunctional peripheral controller 2000 hardware description 2-2 conexant 100723a pll clock generator cpu access interrupt controller cpu core (arm7tdmi) rom/flash bus if (including dram/ flash controller) irq/cpu access dma controller irq/ cpu access scan/print motor controller dma/ irq/ cpu access irq/ cpu access sync/ async serial port prime/battery power and reset control sram/flash cpu access rtc video/scan controller bit rotation dma/ cpu access dram/flash inkjet engine (including inkjet print asic) color scanner host motor drivers p1284 or usb host if irq/ cpu access dma/ cpu access fax modem (optional) cpu access sync serial panel if cache memory controller 1kx32bit (2kx16bit) cache memory icb irq/ cpu access watchdog timer 32-bit isb 32-bit isb 16-bit dab 16-bit and/or 8-bit aeb timing control bi-level resolution conversion dma/ cpu access cpu access serial operator panel if 16-bit ipb gpios and pwm channels cpu access video/color scan ia countach dma controller dram/ sdram controller dram/ sdram 16-bit and/or 8-bit ceb countach subsystem arm bus interface countach subsystem interface countach bus unit video/scan interface ntsc /pal video conexant video chip figure 2-1. MFC2000 organization
multifunctional peripheral controller 2000 MFC2000 100723a conexant 3-1 3. hardware interface 3.1 pin description table 3-1. pin description (1 of 6) pin name pin no. i/o input type output type pin description prtirqn u14 i hu5vt - (hysteresis, pull up) interrupt from the external printing asic (active low) auxclk k20 o - 2xt3v auxiliary clock output for using as the master clock for external devices a[11:0]/a[23:12] a20,b20,b19,b 18,b17,c20,c1 9,c18,c17,d20, d19,d18 i/o 5vt 3xt5vt address bus (12-bit), a[23:12] and a[11:0] are muxed out through same pins. ale c16 o - 2xt5vt address latch output signal for latching a[23:12] externally ae[2]/gpo[14]/sstxd2/ rom_config[0] a19 i/o d5vt 2xt5vt (pull down) address bit for external rom mux in the rom interleave access mode or gpo[14] or tx data output for ssif2 (rom_config[0] input during the reset period) ao[2]/gpo[15]/ssstat2/ro m_config[1] a18 i/o d5vt 2xt5vt (pull down) address bit for external rom mux in the rom interleave access mode or gpo[15] or status input for ssif2 (rom_config[1] input during the reset period) ae[3]/gpo[16]/ clk_config[0] a17 i/o d5vt 2xt5vt (pull down) address bit for external rom mux in the rom interleave access mode or gpo[16] (clk_config[0] input during the reset period) ao[3]/gpo[17]/ clk_config[1] d16 i/o d5vt 2xt5vt (pull down) address bit for external rom mux in the rom interleave access mode or gpo[17] (clk_config[1] input during the reset period) d[15:0] a12,b12,c12,a 13,b13,c13,d1 3,a14,b14,c14, a15,b15,c15,d 15,a16,b16 i/o 5vt 2xt5vt data bus (16-bit) rdn d12 o - 3xt5vt read strobe (active low) wren/doeen b9 o - 4xt5vt write strobe for the lower byte (active low) or dram output enables selects used for non- interleave mode and interleave modes. doeen is used for reading the even address bank (active low). wron/doeon c9 o - 4xt5vt write strobe for the higher byte (active low) or dram output enables selects used for non- interleave mode and interleave modes. doeon is used for reading the odd address bank (active low). romcsn d10 o - 2xt5vt rom chip select (active low) cs[1]n a9 o - 2xt5vt i/o chip select (active low). cs[0]n g18 o 3v 2xt3v sram chip select (active low) (vrtc powered) rasn[1:0] f19,f18 o - 2xt3v dram row address select for bank 0 and 1(active low) (vdram powered) cason[1:0] e17,f20 o - 2xt3v dram column odd address selects used for non- interleave mode and interleave mode. (vdram powered)
MFC2000 multifunctional peripheral controller 2000 hardware description 3-2 conexant 100723a table 3-1. pin description (2 of 6) pin name pin no. i/o input type output type pin description casen[1:0] e20,e19 o - 2xt3v dram column even address selects used for non- interleave mode and interleave mode. (vdram powered) dwrn d17 o - 2xt3v dram write. (vdram powered) dmaack2 k19 o - 1xt5vt external dma acknowledge output (channel 2). dmareq2 f4 i h5vt - (hysteresis) external dma request input (channel 2). fcs0n/pwm[1] d9 o - 2xt5vt flash memory chip select 0 or pwm channel 1 output fcs1n/pwm[2] a8 o - 2xt5vt flash memory chip select 1 or pwm channel 2 output signal. resetn k18 i/o hu5vt 2xt5vt (hysteresis, pull up) MFC2000 reset input/output xin g20 i osc - crystal oscillator input pin for rtc. (vrtc powered) xout h20 o - osc crystal oscillator output pin for rtc. (vrtc powered) pwrdwnn h18 i h3v - (hysteresis) indicate the loss of prime power (result in sysirq). (vrtc powered) wprotn h19 o - 1xt3v write protect during loss of vdd power. note : the functional logic is powered by rtc battery power, but the output drive is powered by dram battery power. (vrtc powered) batrstn g17 i h3v - (hysteresis) battery power reset input. (vrtc powered) ext_pwrdwn_seln g19 i h3v - (hysteresis) external power-down detector select input (active low)(vrtc powered) sc_start[0] v8 o - 1xt3v scanner shift gate control 0 sc_clk1/sc_clk2a u9 o - 1xt3v scanner clock. sc_ledctrl[0] u7 o - 1xt3v scanner led control 0 sc_ledctrl[1]/ sc_start[1] y8 o - 1xt3v scanner led control 1 or scanner shift gate control 1 sc_ledctrl[2]/ sc_start[2] w8 o - 1xt3v scanner led control 2 or scanner shift gate control 2 sstxd1 j19 o - 2xt3v tx data for ssif1 ssrxd1 h17 i hu5vt - (hysteresis, pull up) rx data for ssif1 ssclk1 j20 i/o h5vt 2xt5vt (hysteresis) clock input or output for ssif1 gpio[0]/fwrn/clamp j4 i/o h5vt 2xt5vt (hysteresis) gpio[0] or flash write enable signal for nand-type flash memory or scanner clamp control output gpio[1]/frdn m3 i/o h5vt 2xt5vt (hysteresis) gpio[1] or flash read enable signal for nand-type flash memory. gpio[2]/dmareq1/ ssclk2 v1 i/o h5vt 2xt5vt (hysteresis) gpio[2] or dma channel 1 request input or clock input/output for ssif2. gpio[3]/dmaack1/ ssrxd2 u4 i/o h5vt 2xt5vt (hysteresis) gpio[3] or dma channel 1 acknowledge or rx data for ssif2 gpio[4]/cs[2]n u3 i/o h5vt 2xt5vt (hysteresis) gpio[4] or i/o chip select [2] (active low) gpio[5]/cs[3]n/pwm[3] u2 i/o h5vt 2xt5vt (hysteresis) gpio[5]or i/o chip select [3] (active low) or pwm channel 3 output
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 3-3 table 3-1. pin description (3 of 6) pin name pin no. i/o input type output type pin description gpio[6]/cs[4]n/ eadc_d[3] u1 i/o h5vt 2xt5vt (hysteresis) gpio[6] or i/o chip select [4] (active low) or external adc data [3] input gpio[7]/cs[5]n/ t4 i/o h5vt 2xt5vt (hysteresis) gpio[7] or i/o chip select [5] (active low). gpio[8]/irq[11]/ ssstat1/sc_clk1/2b t3 i/o h5vt 2xt5vt (hysteresis) gpio[8] or external interrupt [11] or status input for ssif1 or scan clock output gpio[9]/irq[13]/ eadc_d[2] t2 i/o h5vt 2xt5vt (hysteresis) gpio[9] or external interrupt [13] or external adc data [2] input gpio[10]/ring_detect/pw m[4] t1 i/o h5vt 2xt5vt (hysteresis) gpio[10] or ring detection input or pwm channel 4 output gpio[11]/cpcin/pwm[0]/alt tone r4 i/o h5vt 2xt5vt (hysteresis) gpio[11] or calling party control input or alttone output gpio[12]/sasclk/ smpwrctrl r3 i/o h5vt 2xt5vt (hysteresis) gpio[12] or clock input/output for sasif or scan motor power control output gpio[13]/sastxd/ pmpwrctrl r2 i/o h5vt 2xt5vt (hysteresis) gpio[13] or tx data output for sasif or print motor power control output gpio[14]/sasrxd/ ringer r1 i/o h5vt 2xt5vt (hysteresis) gpio[14] or rx data input for sasif or ringer output gpio[15]/irq[16]/ sc_clk1/2c p4 i/o h5vt 2xt5vt (hysteresis) gpio[15] or external interrupt [16] or scan clock output gpio[16]/m_txsin p3 i/o h5vt 2xt5vt (hysteresis) gpio[16] or internal modem gpio[17]/m_clkin p2 i/o h5vt 2xt5vt (hysteresis) gpio[17] or internal modem gpio[18]/m_rxout p1 i/o h5vt 2xt5vt (hysteresis) gpio[18] or internal modem gpio[19]/m_sck/mirqn n4 i/o h5vt 2xt5vt (hysteresis) gpio[19] or internal modem or external modem interrupt input gpio[20]/m_strobe/ mcsn n3 i/o h5vt 2xt5vt (hysteresis) gpio[20] or internal modem or external modem chip select gpio[21]/m_cntrl_sin n2 i/o h5vt 2xt5vt (hysteresis) gpio[21] or internal modem gpio[22]/eadc_sample n1 i/o h5vt 2xt5vt (hysteresis) gpio[22] or external adc sample signal output sm[3:0]/ gpo[7:4] v7,w7,y7,u6 o - 1xt3v scan motor control [3:0] pins or gpo[7:4] pins. pm[0]/spi_sid/ eadc_d[0]/gpo[0] u8 i/o 5vt 1xt5vt print motor control [0] output or gpo[0] output or data output for spi or external adc data [0] input pm[1]/spi_sic/ eadc_d[1]/gpo[1] w9 i/o 5vt 1xt5vt print motor control [1] output or gpo[1] output or clock output for spi or external adc data [1] input pm[2]/smi0/gpo[2] y9 o - 1xt3v print motor control [2] output or gpo[2] output or scan motor current control 0. pm[3]/smi1/gpo[3] y12 o - 2xt3v print motor control [3] output or gpo[3] output or scan motor current control 1. tone v9 i/o h5vt 1xt5vt (hysteresis) tone output signal. piodir c1 o - 2xt3v piod[7:0] is output when piodir is high and piod[7:0] is input when piodir is low. stroben a2 i h5vt - (hysteresis) input from pc (active low) autofdn g3 i h5vt - (hysteresis) input from pc (active low) slctinn g2 i h5vt - (hysteresis) input from pc (active low) initn g1 i h5vt - (hysteresis) input from pc (active low) busy a1 o - 2xt3v pio returned status to pc ackn d3 o - 2xt3v pio returned status to pc (active low)
MFC2000 multifunctional peripheral controller 2000 hardware description 3-4 conexant 100723a table 3-1. pin description (4 of 6) pin name pin no. i/o input type output type pin description slctout c3 o - 2xt3v pio returned status to pc pe b2 o - 2xt3v pio returned status to pc faultn b1 o - 2xt3v pio returned status to pc (active low) piod[7:0] d2,d1,c2,h4,h 3,h2,h1,g4 i/o h5vt 2xt5vt (hysteresis) driven by pc or MFC2000 and used to send data or address depending on which mode is used tester_mode j2 i hd5vt - (hysteresis) for test only, it must be ?low? for the normal operation adcrefp y3 i positive reference voltage for the scan padc adcrefn y2 i negative reference voltage for the scan padc power1 y1 i voltage input for power-down detection circuit 1 power2 w4 i voltage input for power-down detection circuit 2 adga y5 - scan padc analog ground adva v5 - scan padc analog power adgd u5 - scan padc digital ground sdaa_spkr v12 o analog telephone line monitoring output from ssd adcv y4 - scan padc internal ground scin w5 i analog scan input signal senin[2:0] v6,w6,y6 i analog sensor inputs for tadc tck w3 i hd5vt - (hysteresis, pull down) test clock input for jtag. it is positive edge-triggered. tms w2 i hu5vt - (hysteresis, pull up) test mode select input for jtag. selects the next state in the tap state machine. trstn w1 i hd5vt - (hysteresis, pull down) suggestion by lauterbach for jtag: connect this signal to resetn in normal mode and disconnect in debug mode. tdi v4 i hu5vt - (hysteresis, pull up) test data input for jtag. serial data input to the jtag shift register. tdo v3 o - 1xt5vt test data output for jtag. serial data output from the jtag shift register. test v2 i hd5vt - (hysteresis, pull down) for test only, it must be ?low? for the normal operation. scanmod j1 i hd5vt - (hysteresis, pull down) for the scan test only, it must be ?low? for normal operations. p80_sel j3 i h3v - p80 dsp test and dft scan mode select, this pin is only used for the test mode. pllref_xin y15 i osc - crystal input pin for pll pllref_xout w15 o - osc crystal output pin for pll pllvdd u15 - +3.3v digital power for pll pllvss u16 - +3.3v digital ground for pll sddata[15:0] n20,p17,p18,p 19,p20,r17,r1 8,r19,r20,t17, t18,t19,t20,u1 7,u18,u19 i/o 5vt 2xt5vt countach (s)dram data bus (16 bits)
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 3-5 table 3-1. pin description (5 of 6) pin name pin no. i/o input type output type pin description sdaddr[12:0] v20,w20,y20, w19,y19,w18, y18,w17,y17,v 16,w16,y16,v1 5 o - 2xt3v countach (s)dram address bus (13 pins) sdcasn u20 o - 2xt3v countach (s)dram column address strobe (active low) sdrasn v19 o - 2xt3v countach (s)dram row address strobe (active low) sdwrn v18 o - 2xt3v countach (s)dram write strobe (active low) sdcsn v17 o - 2xt3v countach (s)dram chip select sdclk100mhz m19 o 5vt 2xt5vt countach (s)dram clock usb_dp b8 i/o positive data input/output pin for usb usb_dn c8 i/o negative data input/output pin for usb sdaa_pwrclk e1 i/o positive power/clock output from ssd sdaa_pwrclkn e2 i/o negative power/clock output from ssd sdaa_dibp e4 i/o positive data input/output pin for sdaa sdaa_dibn e3 i/o negative data input/output pin for sdaa ev_vd[0]/eadc_d[4]/ mreqn w12 i/o 3v 2xt3v external video data [0] input for vip or external adc data [4] input or memory request (active low)-indicates that the following cycle is a memory access. ev_vd[1]/eadc_d[5] u12 i/o 3v 2xt3v external video data [1] input for vip or external adc data [5] input ev_vd[2]/eadc_d[6]/ opcn y13 i/o 3v 2xt3v external video data [2] input for vip or external adc data [6] input or op code fetch (active low)- low indicates that the processor is fetching an instruction from memory. ev_vd[3]/eadc_d[7] w13 i/o 3v 2xt3v external video data [3] input for vip or external adc data [7] input ev_vd[4]/eadc_d[8]/ mas[0] u13 i/o 3v 2xt3v external video data [4] input for vip or external adc data [8] input or memory access size mas[1:0]: 00 - byte, 01 - halfword, 10 - word, 11 - reserved during the normal operation ev_vd[5]/eadc_d[9]/ mas[1] y14 i/o 3v 2xt3v external video data [5] input for vip or external adc data [9] input or memory access size mas[1:0]: 00 - byte, 01 - halfword, 10 - word, 11 - reserved during the normal operation ev_vd[6]/eadc_d[10] w14 i/o 3v 2xt3v external video data [6] input for vip or external adc data [10] input ev_vd[7]/eadc_d11]/ abort v14 i/o 3v 2xt3v external video data [7] input for vip or external adc data [11] input or aborted bus cycle-the address selected is outside of cs?s address ranges. ev_clk v13 i h3v - (hysteresis) external video clock input w_rn n19 o d5vt 2xt5vt (pull down) the bus access is a read operation when w_rn is low and write when w_rn is high. xakn n18 o u5vt 2xt5vt (pull up) siu transaction acknowledge. the d[15:0] data will be transferred during this mclk cycle.
MFC2000 multifunctional peripheral controller 2000 hardware description 3-6 conexant 100723a table 3-1. pin description (6 of 6) pin name pin no. i/o input type output type pin description dmacyc/ clk_config[2] m18 i/o u5vt 2xt5vt (pull up) dma cycle-the dma logic has control of the external bus. (clk_config[2] input during the reset period) waitn j17 o u5vt 2xt5vt (pull up) wait (active low)-reflects the wait states being used by the arm processor. cachehit/ jtag_mode_sel j18 i/o u5vt 2xt5vt (pull up) cache hit-the arm is retrieving data from the cache memory (jtag_mode_sel during the reset period, ?1? ? arm jtag selected seq n17 o d5vt 2xt5vt (pull down) sequential address access. (used with nmreq to indicate memory access type. only required if using co-processor cycles) ssd_dibrx f3 o internal test pin. leave it open. tx_data f2 o internal test pin. leave it open. sdaa_gpio_int f1 o internal test pin. leave it open. vss l1,l2,l3,l4,u1 0,v10,w10,y10, l17,l18,l19,l2 0,a11,b11,c11, d11 - digital ground (16 pins) vdd a10,b10,c10,k 1,k2,k3,k4,u11 ,v11,w11,y11, k17,m20 - +3.3v digital power (13 pins) p80vss m1 - digital ground for p80 dsp p80vdd m2 - +3.3v digital power for p80 dsp vgg1 m17 - +5v power for the +5v tolerant pads vgg2 d14 - +5v power for the +5v tolerant pads vgg3 d5 - +5v power for the +5v tolerant pads vgg4 m4 - +5v power for the +5v tolerant pads vdram e18 - battery power for dram refresh. vrtc f17 - battery power for rtc (nc) a3,b3,a4,b4,c4 ,d4,a5,b5,c5,a 6,b6,c6,d6,a7, b7,c7,d7,d8 - 18 reserved pins
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 3-7 3.2 maximum ratings table 3-2. maximum ratings parameter symbol limits unit vdd digital power vdd -0.5 to +4.6 v battery power vrtc -0.5 to +4.6 v vdram -0.5 to +4.6 v vgg digital power vgg -0.5 to +6.0 v digital gnd gnd -0.5 to +0.5 v digital input (3v) vi -0.5 to +4.6 v digital input (5vt) vi -0.5 to +6.0 v operating temperature range t 0 to 70 o c (commercial) storage temperature range tstg -40 to 80 o c voltage applied to outputs in high z state (3v) vhz -0.5 to 4.6 v voltage applied to outputs in high z state (5vt) vhz -0.5 to 6.0 v static discharge voltage ( 25 o c) esd +2500 v latch-up current ( 25 o c) itrig +400 ma
MFC2000 multifunctional peripheral controller 2000 hardware description 3-8 conexant 100723a 3.3 electrical characteristics table 3-3. digital input characteristics vil vih hysteresis pullup/pulldown resistance symbol description (v min.) (v max.) (v min.) (v max.) (v min.) (k ohms) 3v 3v cmos input 0 0.8 2.0 vdd -- -- u3v 3v cmos input w/pullup 0 0.8 2.0 vdd -- 50-200 h3v 3v cmos input w/hysteresis 0 0.3*vdd 0.7*vdd vdd .5 -- hd3v 3v cmos input w/hysteresis and pull down 0 0.3*vdd 0.7*vdd vdd .5 -- hu3v 3v cmos input w/hysteresis and pullup 0 0.3*vdd 0.7*vdd vdd .5 50-200 h5vt 5v tolerant cmos input w/hysteresis 0 0.3*vdd 0.7*vdd 5.25 .3 -- u5vt 5v tolerant cmos input w/pullup 0 0.3*vdd 0.7*vdd 5.25 -- 50-200 d5vt 5v tolerant cmos input w/pulldown 0 0.3*vdd 0.7*vdd 5.25 -- 50-200 hu5vt 5v tolerant cmos input w/hysteresis and pullup 0 0.3*vdd 0.7*vdd 5.25 .3 50-200 hd5vt 5v tolerant cmos input w/hysteresis and pulldown 0 0.3*vdd 0.7*vdd 5.25 .3 50-200 5vt 5v tolerant cmos input 0 0.8 2.0 5.25 -- -- osc** 3v cmos input 0 0.3*vdd 0.7*vdd vdd -- -- ** these parameters can only be tested under low speed xin clock. table 3-4. output characteristics output type description vol (v max) iol (ma) voh (v min) ioh (ma) cl (pf) 1x3v 1x cmos output, 3v 0.4 -2.0 2.4 2.0 1x5vt 1x cmos output, 5v tolerant 0.4 -2.0 2.4 2.0 1xt5vt 1x cmos output, tristatable, 5v tolerant 0.4 -2.0 2.4 2.0 2x3v 2x cmos output, 3v 0.4 -4.0 2.4 4.0 2xt3v 2x cmos output, tristatable, 3v 0.4 -4.0 2.4 4.0 2x5vt 2x cmos output, 5v tolerant 0.4 -4.0 2.4 4.0 2xt5vt 2x cmos output, tristatable, 5v tolerant 0.4 -4.0 2.4 4.0 3xt3v 3x cmos output, 3v 0.4 -8.0 2.4 8.0 3xt5vt 3x cmos output, tristatable, 5v tolerant 0.4 -8.0 2.4 8.0 4xt5vt 4x cmos output, tristatable, 5v tolerant 0.4 -12.0 2.4 12.0
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 3-9 table 3-5. power supply requirements operating voltage current* symbol description min. (v) max. (v) typ. @ 25 c(ma) max.@ 0 c (ma) vgg digital power for 5vt 4.75 5.25 vdd digital power 3.0 3.6 gnd digital gnd 0 0 idd total digital current (tbd) (tbd) vbat battery power 2.7 3.6 vdram battery power 2.7 3.6 note: * maximum power supply current is measured at 3.6v. table 3-6. battery power supply current requirements vbat vdram operating voltage (v) typ.@25 c ( a) max.@70 c ( a) typ.@25 c ( a) max.@70 c ( a) 2.7 4 tbd 100 tbd 3.0 tbd tbd tbd tbd 3.3 6 tbd tbd tbd 3.6 tbd tbd tbd tbd note: battery power supply current is measured when a 32khz crystal is used. the dram battery currents that are listed are somewhat dependent on the type of dram used. this particular configuration had 1 interleaved dram bank in backup mode.
MFC2000 multifunctional peripheral controller 2000 hardware description 3-10 conexant 100723a 3.4 pin layout MFC2000 chip bottom view a b c d e f g h j k l m n p r t u v w y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 3-1. MFC2000 bga bottom view
multifunctional peripheral controller 2000 MFC2000 100723a conexant 4-1 4. cpu and bus interface 4.1 memory map and chip select description 4.1.1 memory map the arm7tdmi core is capable of directly accessing 4 gb of memory (a31-a0). the MFC2000 is designed to directly access 64-mb of memory composed of internal and external memory spaces by means of the 26-bit system address bus (a25-a0). the MFC2000 internally decodes address range 00000000h-03ffffffh (64 m). address range 01000000h-01ffffffh (16 m) is arranged for the internal registers/memory and external countach imaging dsp subsystem memory. address range 00000000h-00ffffffh (16 m) and address range 02000000h-03ffffffh (32 m) are arranged for the external device/memory use on the arm bus. only 24 address lines (a23-a0) are brought out of the MFC2000 chip, and the lower half and the higher half are multiplexed through the same 12 pins. the 16 mb address range (maximum) can be decoded externally, if necessary. figure 4-1 and figure 4-2 show the MFC2000 memory map with memory type designations and locations and provides memory segmentation into select signal ranges. 4.1.1.1 internal memory space the MFC2000 internal memory occupies 128 kb of the address range from 01fe0000h through 01fffffh). internal memory space includes the following: cache memory space (64 kb) (01fe0000h-01feffffh) (reserved space) (32 kb) (01ff0000h-01ff7fffh) internal register space (4 kb) (01ff8000h-01ff8fffh) internal ram space (28 kb) (01ff9000h-01ffffffh) the cache memory space includes the following: 1. the cache memory (4096 bytes) (01fe0000h-01fe0fffh) 2. the tag memory (4096 bytes) (01fe1000h-01fe1fffh) 3. (reserved) (56 kb) (01fe2000h-01feffffh) the internal register address range consists of 3 sections: 1. the first (lowest) section (01ff8000h to 01ff87ffh, 2 kb), is reserved for operational registers, i.e., those that are modified during normal operation, but which are not intended to require firmware initialization after reset. 2. the second section (01ff8800h to 01ff8dffh, 1.5 kb) contains the setup registers, i.e., those that are generally written only once for system initialization after reset. 3. the third section (01ff8e00h to 01ff8fffh, 512 bytes) is reserved for testing purposes. note : all internal register accesses are two cpuclk-cycle operations.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-2 conexant 100723a the internal ram space includes the following: 1. bit rotation ram area bit rotation ram: 512 halfwords (1 kb) (01ff9000h-01ff93ffh) (reserved) (3072 bytes) (01ff9400h-01ff9fffh) 2. countach subsystem memory area countach scratch pad (512 bytes) (256 halfwords)(01ffa000h-01ffa1ffh) countach data dma channel 0 (1 halfword) (01ffa200h-01ffa201h) countach data dma channel 1 (1 halfword) (01ffa202h-01ffa203h) countach data dma channel 2 (1 halfword) (01ffa204h-01ffa205h) countach data dma channel 3 (1 halfword) (01ffa206h-01ffa207h) reserved (344 bytes) (01ffa208h-01ffa35fh) countach program dma address (5 bytes) (01ffa360h-01ffa364h) reserved (155 bytes) (01ffa365h-01ffa3ffh) vsi buffer (256 bytes) (2x64 halfwords) (01ffa400h-01ffa4ffh) (reserved) (23296 bytes) (01ffa500h-01ffffffh) 4.1.1.2 external countach imaging dsp subsystem memory space the external memory space (8 mb) is allocated to the external dram/sdram on the countach imaging dsp bus subsystem. countach imaging dsp subsystem sdram/dram (8 m) (01000000h-017fffffh)
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-3 4.1.1.3 external memory space the external memory space (up to 48 m) consists of rom, dram/aram, flash memory, sram, modem, and variable-use spaces with assigned chip selects. most external chip selects have programmable address ranges, start locations, wait states, and read and write strobe timing. sram and dram/aram chip select controls are battery-backed up. refer to figure 4-1 for the MFC2000 memory map and to figure 4-2 for the internal memory map. external memory spaces include the following: romcsn, rom (4 m) (00000000h-003fffffh) cs5n, general (4 m) (00400000h-007fffffh) fcs0n, nor type flash memory (2 m) (00800000h-009fffffh) fcs1n, nor type flash memory (2 m) (00a00000h-00bfffffh) address location for generating fwrn and frdn for the nand type flash memory (00c00000h-00c0003fh) (reserved) (00c00002h-00c1ffffh) mcsn, modem (128 k) (00c20000h-00c2ffffh) p80_csn (00c30000h - 00c37fffh) sdaa_csn (00c38000h - 00c3ffffh) cs4n, optional general (128 k) (00c40000h-00c5ffffh) cs3n, optional general (128 k) (00c60000h-00c7ffffh) cs2n, optional general (512 k) (00c80000h-00cfffffh) cs1n, general (1 m) (00d00000h-00dfffffh) cs0n, sram or general (2 m) (00e00000h-00ffffffh) sdram (for internal and countach imaging dsp subsystem) (16 m) (01000000h-01ffffffh) ras0n, dram or aram (16 m) (02000000h-02ffffffh) ras1n, dram or aram (16 m) (03000000h-03ffffffh)
MFC2000 multifunctional peripheral controller 2000 hardware description 4-4 conexant 100723a table 4-1. fixed-location and size chip selects chip select device romcsn rom fcs1n/fcs0n nand- or nor-type flash memory cs0n sram, or other cs1n (optional) general use optional mcsn (optional) external fax modem (optional) cs2n i/o devices, or other cs3n (optional) general use cs4n (optional0 general use cs5n 4 mb rom, sram, or other dram/aram chip selects can also be programmed to 1 of 4 sizes (from 512 k to 16 m). rom chip select (romcsn) romcsn selects external rom located in 4-mb address space 00000000h-003fffffh, and is active for read and write accesses. the romctrl register can be used to select 0 to 7 (default) wait states, and 0 or 1 (default) read and write strobe on delays. for customers that choose to use nor-type flash memory in the rom address area, the write operation is also allowed in the rom address area. chip select 5 (cs5n) cs5n is an active read/write select signal for the 4 mb address range (00400000h to 007fffffh) directly below the romcsn address range. the cs5ctrl register can be used to select 0 to 7 (default) wait states, and 0 or 1 (default) read and write strobe on delays. gpio[7] (default) can be configured as cs5n using the gpio[7]/cs5n bit of the gpioconfig register. sram chip select 0 (cs0n) cs0n is designed for use in selecting external sram, but can also be used for other purposes. it has 2 mb address range (00e00000h to 00ffffffh). the cs0n can also be programmed for 0 (default) to 7 wait states, 0 (default) or 1 read and write strobe on delays, and normal (default) or early write strobe off times using the cs0ctrl register. dram chip select (rasn[1:0], cason[1:0] and casen[1:0]) dram address space can be selected in 2 separate memory blocks (bank 0: rasn[0] and bank 1: rasn[1]). separate control bits are provided in the backup configuration register to enable and disable each of the memory banks (default: bank0 is enabled and 8-bit dram is selected). non-interleaved dram accesses and 2-way interleaved dram accesses are supported. cason[1:0] and casen[1:0] are used differently for different access modes. rasn is asserted before casn for normal read and write operations. also, ras can be kept active and casn is toggled to do burst mode operations. casn-before-rasn refresh mode is the only refresh mode for mfc2k (for more dram information, see the dram controller section.) the address ranges of the two memory banks (ras0n and ras1n) are continuous around the midpoint of the dram memory bank. the rasn[1] starting address is 03000000h and grows larger based on the size of the memory. the end of the rasn[0] bank ends at 03000000h and grows smaller from that point. each bank has separate configuration controls. the memory range is programmed through the address multiplexer selections for bank 0 and bank 1 in the dramctrl register.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-5 flash memory chip selects (fcs1n and fcs2n) fcs0n and fcs1n are multiplexed with pwm[1] and pwm[2] and output through fcs0n/pwm[1] and fcs1n/pwm[2] pins. after reset, the flash disable bit (bit 0) of the flashctrl register is 0 and the fcs0n/pwm[1] and fcs1n/pwm[2] pins are used as fcs0n and fcs1n. fcs0n and fcs1n can access either nor-type (default) or nand-type flash memory, selectable with the nandflashenb bit (bit 6) of the flashctrl register. when enabled for nor-type flash memory (default), fcs1n can be activated by accessing the 2-mb (00a00000h-00bfffffh) flash memory address area. fcs0n can be activated by accessing the 2-mb (00800000h - 009fffffh) flash memory address area. firmware controls the flash memory access block size. if enabled for nand-type flash memory, fcs0n and fcs1n revert to the gpo function and output bit 9 and bit 8 values of the flashctrl register . 0 to 7 (default) wait states and normal (default) or early off of the write strobe can be chosen using the flashctrl register described in the siu section. modem chip select (mcsn) the 128 kb address space from 00c20000h to 00c2ffffh is reserved for the external modem and selected with mcsn. it is muxed with the m_strobe signal of the modem ia on the pin. m_strobe is usually used to interface the embedded dsp to the external modem ia if the embedded v.34 modem dsp is used. mcsn can be selected and muxed out for the external modem if the embedded modem dsp is not used. mcsn can be programmed for 0 to 7 (default) wait states, 0 (default) or 1 read and write strobe on delays, and normal (default) or early write strobe off times using the mcsctrl register. p80 chip select (p80_csn) address space form 00c3000 to 00c7fff has been reserved for the p80 functions. smart data access arraignment (sdaa_csn) address space form 00c3800 to 00cffff has been reserved for the sdaa functions. 4.1.1.4 external i/o chip selects chip select [2] (cs2n) the 512 kb address space from 00c80000h to 00cfffffh is selected using the external i/o chip selects cs2n. gpio[4] (default) can be configured as cs2n using the gpio[4]/cs2n bit of the gpioconfig register. cs2n can be programmed for 0 (default) to 7 wait states, 0 (default) to 3 read and write strobe delays, and normal (default) or early write strobe off times using the cs2ctrl register. chip select [4:3] (cs4n-cs3n)(optional) the 256 kb address space from 00c40000h to 00c7ffffh can optionally be selected using the two external i/o chip selects cs4n and cs3n. these chip selects are configured identically to cs2n. gpio[6] (default) can be configured as cs4n using the gpio[6]/cs4n bit of the gpioconfig register. likewise, gpio[5] (default) can be configured as cs3n by using the gpio[5]/cs3n bit in the gpioconfig1 register. the top 128 kb (00c40000h to 00c5ffffh) are addressed by cs4n. cs4n is active for read-access only (internally gated with the read strobe) when the cs4nreadonly bit (bit 8) of the siuconfig register is 1. cs4n is active for both read and write access when the cs4nreadonly bit (bit 8) of the siuconfig register is 0. the next 128 kb (00c60000h to 00c7ffffh) is addressed by cs3n. cs3n is active for write-access only (internally gated with the write even strobe) when the cs3nwriteonly bit (bit 7) of the siuconfig register is 1. if the external i/o device using cs3n is a 16-bit device, 16-bit access must be done. no high-byte or low-byte access can be done. cs3n is active for both read and write access when the cs3nwriteonly bit (bit 7) of the siuconfig register is 0. chip select 1 (cs1n) the next address range below those of cs4n-cs2n is the 1-mb range (00d00000h to 00dfffffh) selected by cs1n. cs1n can be programmed for 0 (default) to 7 wait states, 0 (default) to 3 read and write strobe delays, and normal (default) or early write strobe off times using the cs1ctrl register.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-6 conexant 100723a romcsn 007fffff 02ffffff 00000000 003fffff imemcs 01ffffff csn[5] iiocs ics csn[0] fcs1n fcs0n 009fffff 00bfffff 00c3ffff 00c5ffff 00c7ffff 00cfffff 00dfffff 00ffffff 03ffffff csn[1] csn[2] csn[3] csn[4] mcsn 01fdffff (reserved) (reserved) 01fdffff 01ff7fff 01ffffff 01ff8fff cachecs 01feffff rasn[1] rasn[0] rasn[0] sdram 017fffff (reserved) 00c1ffff (reserved) 00c0003f nand flash registers figure 4-1. MFC2000 memory map
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-7 (reserved) iiocs imemcs iiocs 01ffa3ff 01ffffff 01ff8fff 01ff7fff 01ff87ff 01ff8df f 01ff8ff f (reserved) bit rotation buffer 01ff93ff (reserved) (reserved) c cachecs 01fdffff cache memory 01fe0fff tag memory 01fe1fff rasn[0] countach scratchpad vsi buffer 01ffa000 01ffa4ff figure 4-2. MFC2000 internal memory map
MFC2000 multifunctional peripheral controller 2000 hardware description 4-8 conexant 100723a 4.1.2 register map table 4-2. operation register map (1 of 9) operation registers are located from 01ff8000h to 01ff87ffh. address register name block name r, dr (dummy read), w, dw (dummy write) 01ff8000-01 tadcctrl tadc r/w 01ff8002-03 tadcinsdata tadc r 01ff8004-05 tadcch0data tadc r 01ff8006-07 tadcch1data tadc r 01ff8008-09 tadcch2data tadc r 01ff800a-1f (not used) ?? 01ff8020-21 irqfiqevent1 interrupt controller r 01ff8022-23 irqfiqevent2 interrupt controller r(bit[6:2], bit[0]) r/w(bit[1]) 01ff8024-25 irqenable1 interrupt controller r/w 01ff8026-27 irqenable2 interrupt controller r/w 01ff8028-29 fiqenable1 interrupt controller r/w 01ff802a-2b fiqenable2 interrupt controller r/w 01ff802c-2d eirqconfigclr interrupt controller r/w 01ff802e-2f irqtimer1 interrupt controller r/w 01ff8030-31 irqtimer2 interrupt controller r/w 01ff8032-3f (not used) ?? 01ff8040 watchdogenretrigger watchdog timer w 01ff8042 watchdoginterval watchdog timer r/w 01ff8044 hwversion watchdog timer r 01ff8046 productcode watchdog timer r 01ff8048-4b (not used) ?? 01ff804c-4d sscurtimer1 scan/print motor controller r/w 01ff804e-4f sscurtimer2 scan/print motor controller r/w 01ff8050-51 sstepctrl scan/print motor controller r/w 01ff8052-53 ssteptimer scan/print motor controller r/w 01ff8054-55 ssdelaytimer scan/print motor controller r/w 01ff8056-57 smpattern/gpo scan/print motor controller r/w 01ff8058-59 vpstepctrl scan/print motor controller r/w 01ff805a-5b vpsteptimer scan/print motor controller r/w 01ff805c-5d vpmpattern/gpo scan/print motor controller r/w 01ff805e-5f (not used) ?? 01ff8060-61 rotctrl bit rotation block r/w 01ff8062-63 rotpackeddata bit rotation block r/w 01ff8064-67 (not used) ?? 01ff8069-6b totalbindatcntr bi-level resolution conversion r 01ff806c-6d firstblkdatcnt bi-level resolution conversion r 01ff806e-6f lastblkdatcnt bi-level resolution conversion r 01ff8070-71 bircinfifo0 bi-level resolution conversion r/w
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-9 table 4-2. operation register map (2 of 9) address register name block name r, dr (dummy read), w, dw (dummy write) 01ff8072-73 bircinfifo1 bi-level resolution conversion r/w 01ff8074-75 bircinfifo2 bi-level resolution conversion r/w 01ff8076-77 bircinfifo3 bi-level resolution conversion r/w 01ff8078-79 bircinhold bi-level resolution conversion r/w 01ff807a-7b bircinfifoctrl bi-level resolution conversion r/w 01ff807c-7d biresconratio bi-level resolution conversion r/w 01ff807e-7f biresconctrl bi-level resolution conversion r/w 01ff8080-81 bircoutfifo0 bi-level resolution conversion r/w 01ff8082-83 bircoutfifo1 bi-level resolution conversion r/w 01ff8084-85 bircoutfifo2 bi-level resolution conversion r/w 01ff8086-87 bircoutfifo3 bi-level resolution conversion r/w 01ff8088-89 bircouthold bi-level resolution conversion r/w 01ff808a-8b bircoutfifoctrl bi-level resolution conversion r/w 01ff808c-8d singlingmask bi-level resolution conversion r/w 01ff808e-8f hszerono bi-level resolution conversion r/w 01ff8090-1 sec_min battery rtc r(bit[7]), r/dw(bit[5:0]) r(bit[15]), r/dw(bit[13:8]) 01ff8092-3 hour_day battery rtc r(bit[7]), r/dw(bit[4:0]) r(bit[15]), r/dw(bit[12:8]) 01ff8094-5 month_year battery rtc r(bit[7]), r/dw(bit[3:0]) r(bit[15]), r/dw(bit[12:8]) 01ff8096-7 rtcctrl battery rtc dr/dw 01ff8098-9 backupconfig battery rtc r/w 01ff809a-f (not used) ?? 01ff80a0-1 lockenb prime power reset logic dw 01ff80a2-7 (not used) ?? 01ff80a8-9 cpcthreshold cpc logic r/w 01ff80aa-b cpcstatctrl cpc logic r/w 01ff80ac-f (not used) ?? 01ff80b0-1 tonegenf1 tonegen block r/w 01ff80b2-3 alttonegen tonegen block r/w 01ff80b4-5 bellctrl bell ringer r/w 01ff80b6-7 bellperiod bell ringer r/w 01ff80b8-9 bellphase bell ringer r/w 01ff80ba-b tonegenf2 tonegen block r/w 01ff80bc-d tonegenswitch tonegen block r/w 01ff80be-f tonegentotal tonegen block r/w 01ff80c0-c1 pwmch0ctrl pwm logic r/w 01ff80c2-c3 pwmch1ctrl pwm logic r/w 01ff80c4-c5 pwmch2ctrl pwm logic r/w 01ff80c6-c7 pwmch3ctrl pwm logic r/w
MFC2000 multifunctional peripheral controller 2000 hardware description 4-10 conexant 100723a table 4-2. operation register map (3 of 9) address register name block name r, dr (dummy read), w, dw (dummy write) 01ff80c8-c9 pwmch4ctrl pwm logic r/w 01ff80ca-cf (not used) ?? 01ff80d0-df (not used) ?? 01ff80e0-ef (reserved) ? ? 01ff80f0-1 sascmd sasif r/w 01ff80f2-3 sasdata sasif r/w 01ff80f4-5 sasdiv sasif r/w 01ff80f6-7 (not used) ?? 01ff80f8-9 sasirqsts sasif r/w 01ff80fa-ff (not used) ?? 01ff8100 sscmd ssif r/w 01ff8102 ssdata ssif r/w 01ff8104 ssdiv ssif r/w 01ff8106-07 (not used) ?? 01ff8108-09 sscmd2 ssif2 r/w 01ff810a-0b ssdata2 ssif2 r/w 01ff810c-0d ssdiv2 ssif2 r/w 01ff810e-0f (not used) ?? 01ff8110-11 t4datafifo0 t4/t6 block r/w 01ff8112-13 t4datafifo1 t4/t6 block r/w 01ff8114-15 t4datafifo2 t4/t6 block r/w 01ff8116-17 t4datafifo3 t4/t6 block r/w 01ff8118-19 t4datahold t4/t6 block r/w 01ff811a-1b t4datafifoctrl t4/t6 block r/w 01ff811c-1d t4dataport t4/t6 block r/w 01ff811e-1f t4dataporttfr t4/t6 block r/w 01ff8120-4f (not used) ?? 01ff8150-51 t4refdatafifo0 t4/t6 block r/w 01ff8152-53 t4refdatafifo1 t4/t6 block r/w 01ff8154-55 t4refdatafifo2 t4/t6 block r/w 01ff8156-57 t4refdatafifo3 t4/t6 block r/w 01ff8158-59 t4refdatahold t4/t6 block r/w 01ff815a-5b t4refdatafifoctrl t4/t6 block r/w 01ff815c-5d t4refdataport t4/t6 block r/w
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-11 table 4-2. operation register map (4 of 9) address register name block name r, dr (dummy read), w, dw (dummy write) 01ff815e-5f t4refdataporttfr t4/t6 block r/w 01ff8160-61 t4curdatafifo0 t4/t6 block r/w 01ff8162-63 t4curdatafifo1 t4/t6 block r/w 01ff8164-65 t4curdatafifo2 t4/t6 block r/w 01ff8166-67 t4curdatafifo3 t4/t6 block r/w 01ff8168-69 t4curdatahold t4/t6 block r/w 01ff816a-6b t4curdatafifoctrl t4/t6 block r/w 01ff816c-6d t4curdataport t4/t6 block r/w 01ff816e-6f t4curdataporttfr t4/t6 block r/w 01ff8170-71 t4config t4/t6 block r/w 01ff8172-73 t4control t4/t6 block r/w 01ff8174-75 t4 status t4/t6 block r 01ff8176-77 t4intmask t4/t6 block r/w 01ff8178-79 t4bytes t4/t6 block r/w 01ff817a-7b t4fifobitrem t4/t6 block r/w 01ff817c-7f (not used) ?? 01ff8180-81 (not used) ?? 01ff8182-83 dma1config dma controller r/w 01ff8184-85 dma1cntlo dma controller r/w 01ff8186-87 dma1cnthi dma controller r/w 01ff8188-89 dma2cntlo dma controller r/w 01ff818a-8b dma2cnthi dma controller r/w 01ff818c-8d dma2bufcntlo dma controller r/w 01ff818e-8f dma2bufcnthi dma controller r/w 01ff8190-91 dma3cntlo dma controller r/w 01ff8192-93 dma3cnthi dma controller r/w 01ff8194-95 dma4cntlo dma controller r/w 01ff8196-97 dma4cnthi dma controller r/w 01ff8198-99 dma5cntlo dma controller r/w 01ff819a-9b dma5cnthi dma controller r/w 01ff819c-9d dma6cntlo dma controller r/w 01ff819e-9f dma6cnthi dma controller r/w 01ff81a0-a1 dma7cntlo dma controller r/w 01ff81a2-a3 dma7cnthi dma controller r/w 01ff81a4-a5 dma8cntlo dma controller r/w 01ff81a6-a7 dma8cnthi dma controller r/w 01ff81a8-a9 dma9cntlo dma controller r/w 01ff81aa-ab dma9cnthi dma controller r/w 01ff81ac-ad dma10cntlo dma controller r/w 01ff81ae-af dma10cnthi dma controller r/w
MFC2000 multifunctional peripheral controller 2000 hardware description 4-12 conexant 100723a table 4-2. operation register map (5 of 9) address register name block name r, dr (dummy read), w, dw (dummy write) 01ff81b0-b1 dma0config dma controller r/w 01ff81b2-b3 dma2config dma controller r/w 01ff81b4-b5 dma2blksize dma controller r/w 01ff81b6-b7 dma2bufblksize dma controller r/w 01ff81b8-b9 (not used) ?? 01ff81ba-bb dma5blksize dma controller r/w 01ff81bc-bd dma6/10throttle dma controller r/w 01ff81be-bf dma9blksize dma controller r/w 01ff81c0-c1 dma10blksize dma controller r/w 01ff81c2-c3 dmaincconfig dma controller r/w 01ff81c4-c5 dmacntenbconfig dma controller r/w 01ff81c6-c7 dmaendian dma controller r/w 01ff81c8-c9 dmausb0cntlo dma controller r/w 01ff81ca-cb dmausb0cnthi dma controller r/w 01ff81cc-cd dmausb0blksiz dma controller r/w 01ff81ce-cf dmausb1cntlo dma controller r/w 01ff81d0-d1 dmausb1cnthi dma controller r/w 01ff81d2-d3 dmausb1blksiz dma controller r/w 01ff81d4-d5 dmausb2cntlo dma controller r/w 01ff81d6-d7 dmausb2cnthi dma controller r/w 01ff81d8-d9 dmausb2blksiz dma controller r/w 01ff81da-db dmausb3cntlo dma controller r/w 01ff81dc-dd dmausb3cnthi dma controller r/w 01ff81de-df dmausb3blksiz dma controller r/w 01ff81e0-e1 dma11cntlo dma controller r/w 01ff81e2-e3 dma11cnthi dma controller r/w 01ff81e4-e5 dma11blksiz dma controller r/w 01ff81e6-e7 dma12cntlo dma controller r/w 01ff81e8-e9 dma12cnthi dma controller r/w 01ff81ea-eb dma12blksiz dma controller r/w 01ff81ec-ff (not used) ?? 01ff8200-01 pioctrl pio r/w 01ff8202-03 pioif pio r/w 01ff8204-05 piodata pio r/w 01ff8206-07 pioackpw pio r/w 01ff8208-09 piorevdatasts pio r/w 01ff820a-0b piodatabussts pio r/w 01ff820c-0d piohosttimeout pio r/w 01ff820e-0f pioirqsts pio r/w 01ff8210-11 pioirqmask pio r/w
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-13 table 4-2. operation register map (6 of 9) address register name block name r, dr (dummy read), w, dw (dummy write) 01ff8212-13 piofifoif pio r/w 01ff8214-1f (not used) ?? 01ff8220-21 piooutfifo0 pio r/w 01ff8222-23 piooutfifo1 pio r/w 01ff8224-25 piooutfifo2 pio r/w 01ff8226-27 piooutfifo3 pio r/w 01ff8228-29 pioouthold pio r/w 01ff822a-2b piooutfifoctrl pio r/w 01ff822c-2f (not used) ?? 01ff8230-31 pioinfifo0 pio r/w 01ff8232-33 pioinfifo1 pio r/w 01ff8234-35 pioinfifo2 pio r/w 01ff8236-37 pioinfifo3 pio r/w 01ff8238-39 pioinhold pio r/w 01ff823a-3b pioinfifoctrl pio r/w 01ff823c-4f (not used) ?? 01ff8250-5b (not used) ?? 01ff825c-5d vshiaddr1 countach bus system - cdmac r/w 01ff825e-5f vsloaddr1 countach bus system - cdmac r/w 01ff8260-61 vshiaddr2 countach bus system - cdmac r/w 01ff8262-63 vsloaddr2 countach bus system - cdmac r/w 01ff8264-65 vshiaddrstep countach bus system - cdmac r/w 01ff8266-67 vsloaddrstep countach bus system - cdmac r/w 01ff8268-69 vsmode countach bus system - cdmac r/w 01ff826a-6b abc2ablksiz countach bus system - cdmac r/w 01ff826c-6d aba2chiaddr countach bus system - cdmac r/w 01ff826e-6f aba2cloaddr countach bus system - cdmac r/w 01ff8270-71 abc2ahiaddr countach bus system - cdmac r/w 01ff8272-73 abc2aloaddr countach bus system - cdmac r/w 01ff8274-75 aba2cthrottle countach bus system - cdmac r/w 01ff8276-77 abc2athrottle countach bus system - cdmac r/w 01ff8278-7f (not used) ?? 01ff8280-81 dramconfig countach bus system - sdramc r/w 01ff8282-83 abiirqstat countach bus system - abi r/w 01ff8284-85 abiirqenable countach bus system - abi r/w 01ff8286-87 abicountachctrl countach bus system - abi r/w 01ff8288-89 vsimode countach bus system - vsi r/w 01ff828a-a7 (not used) ?? 01ff82a8-a9 defrdhiaddr countach bus system - cbu r/w 01ff82aa-ab defrdloaddr countach bus system - cbu r/w
MFC2000 multifunctional peripheral controller 2000 hardware description 4-14 conexant 100723a table 4-2. operation register map (7 of 9) address register name block name r, dr (dummy read), w, dw (dummy write) 01ff82ac-ad defwrhiaddr countach bus system ? cbu r/w 01ff82ae-af defwrloaddr countach bus system ? cbu r/w 01ff82b0-b1 defrddata countach bus system ? cbu r/w 01ff82b2-b3 defwrdata countach bus system ? cbu r/w 01ff82b4-ff (not used) ?? 01ff8300-01 abia2cbuff1 countach bus system ? abi r/w 01ff8302-03 abia2cbuff2 countach bus system ? abi r/w 01ff8304-05 abia2cbuff3 countach bus system ? abi r/w 01ff8306-07 abia2cbuff4 countach bus system ? abi r/w 01ff8308-09 abic2abuff1 countach bus system ? abi r/w 01ff830a-0b abic2abuff2 countach bus system ? abi r/w 01ff830c-0d abic2abuff3 countach bus system ? abi r/w 01ff830e-0f abic2abuff4 countach bus system ? abi r/w 01ff8310-11 csidmabuff1 countach bus system ? csi r/w 01ff8312-13 csidmabuff2 countach bus system ? csi r/w 01ff8314-15 csidmabuff3 countach bus system ? csi r/w 01ff8316-17 csidmabuff4 countach bus system ? csi r/w 01ff8318-ff (not used) ?? 01ff8400-ff (not used) ?? 01ff8500-3f (not used) ?? 01ff8540-41 scanctrl video/scan controller r/w 01ff8542-43 scanctrlstat video/scan controller r only 01ff8544-45 vscirqstatus video/scan controller r/w 01ff8546-47 vscctrl video/scan controller r/w 01ff8548-49 vidcapturectrl video/scan controller r/w (bit[8] - r only) 01ff854a-4b spi_ctrl video/scan controller r/w (bit[8] - r only) 01ff854c-4d spi_stat video/scan controller r only 01ff854e-7f (not used) ?? 01ff8580-81 usbep1fifo1 usb interface r/w 01ff8582-83 usbep1fifo2 usb interface r/w 01ff8584-85 usbep1fifo3 usb interface r/w 01ff8586-87 usbep1fifo4 usb interface r/w 01ff8588-89 usbep1hold usb interface r/w 01ff858a-8b usbep1ctrl usb interface r/w 01ff858c-8d usbep1data usb interface r/w 01ff858e-8f usbep1tran usb interface r/w 01ff8590-9f (not used) ?? 01ff85a0-a1 usbep2fifo1 usb interface r/w 01ff85a2-a3 usbep2fifo2 usb interface r/w 01ff85a4-a5 usbep2fifo3 usb interface r/w 01ff85a6-a7 usbep2fifo4 usb interface r/w 01ff85a8-a9 usbep2hold usb interface r/w
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-15 table 4-2. operation register map (8 of 9) address register name block name r, dr (dummy read), w, dw (dummy write) 01ff85aa-ab usbep2ctrl usb interface r/w 01ff85ac-ad usbep2data usb interface r/w 01ff85ae-af usbep2tran usb interface r/w 01ff85b0-b1 usbep3fifo1 usb interface r/w 01ff85b2-b3 usbep3fifo2 usb interface r/w 01ff85b4-b5 usbep3fifo3 usb interface r/w 01ff85b6-b7 usbep3fifo4 usb interface r/w 01ff85b8-b9 usbep3hold usb interface r/w 01ff85ba-bb usbep3ctrl usb interface r/w 01ff85bc-bd usbep3data usb interface r/w 01ff85be-bf usbep3tran usb interface r/w 01ff85c0-c1 usbep4fifo1 usb interface r/w 01ff85c2-c3 usbep4fifo2 usb interface r/w 01ff85c4-c5 usbep4fifo3 usb interface r/w 01ff85c6-c7 usbep4fifo4 usb interface r/w 01ff85c8-c9 usbep4hold usb interface r/w 01ff85ca-cb usbep4ctrl usb interface r/w 01ff85cc-cd usbep4data usb interface r/w 01ff85ce-cf usbep4tran usb interface r/w 01ff85d0-d1 usbep0buf12 usb interface r/w 01ff85d2-d3 usbep0buf34 usb interface r/w 01ff85d4-d5 usbep0buf56 usb interface r/w 01ff85d6-d7 usbep0buf78 usb interface r/w 01ff85d8-d9 usbvenbuf12 usb interface r/w 01ff85da-db usbvenbuf34 usb interface r/w 01ff85dc-dd usbvenbuf56 usb interface r/w 01ff85de-df usbvenbuf78 usb interface r/w 01ff85e0-e1 usbvenstdat12 usb interface r/w 01ff85e2-e3 usbvenstdat34 usb interface r/w 01ff85e4-e5 usbvenstdat56 usb interface r/w 01ff85e6-e7 usbvenstdat78 usb interface r/w 01ff85e8-e9 usbdesadr usb interface r/w 01ff85ea-eb usbirq usb interface r/w 01ff85ec-ed usbsoftreset usb interface w 01ff85ee-ef usbstall usb interface w 01ff85f0-f1 usbpostdat1/2 usb interface r 01ff85f2-f3 usbpostdat3/4 usb interface r 01ff85f4-f5 usbpostdat5/6 usb interface r 01ff85f6-f7 usbpostdat7/8 usb interface r 01ff85f8-ff (not used) usb interface ? 01ff85ec-ff (not used) ??
MFC2000 multifunctional peripheral controller 2000 hardware description 4-16 conexant 100723a table 4-2. operation register map (9 of 9) address register name block name r, dr (dummy read), w, dw (dummy write) 01ff8600-01 sastxfifohw0 sasif r/w 01ff8602-03 sastxfifohw1 sasif r/w 01ff8604-05 sastxfifohw2 sasif r/w 01ff8606-07 sastxfifohw3 sasif r/w 01ff8608-09 sastxfifohw4 sasif r/w 01ff860a-0b sastxfifohw5 sasif r/w 01ff860c-0d sastxfifohw6 sasif r/w 01ff860e-0f sastxfifohw7 sasif r/w 01ff8610-11 sasrxfifohw0 sasif r/w 01ff8612-13 sasrxfifohw1 sasif r/w 01ff8614-15 sasrxfifohw2 sasif r/w 01ff8616-17 sasrxfifohw3 sasif r/w 01ff8618-19 sasrxfifohw4 sasif r/w 01ff861a-1b sasrxfifohw5 sasif r/w 01ff861c-1d sasrxfifohw6 sasif r/w 01ff861e-1f sasrxfifohw7 sasif r/w 01ff8620-7ff (not used) ??
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-17 table 4-3. setup registers (1 of 2) setup registers are located from 01ff8800h to 01ff8dffh. address register name block name r, dr (dummy read), w, dw (dummy write) 01ff8800-01 siuconfig siu r/w 01ff8802-03 romctrl siu r/w 01ff8804-05 cs0/cs5ctrl siu r/w 01ff8806-07 cs1/2ctrl siu r/w 01ff8808-09 mcsctrl siu r/w 01ff880a-0b flashctrl siu r/w 01ff880c-0d rotpackctrl siu r/w 01ff880e-0f cs3/4ctrl siu r/w 01ff8820-21 dramctrl dram/flash memory controller r/w 01ff8822-2f (not used) ?? 01ff8830-31 gpioconfig gpio block r/w 01ff8832-33 gpiodata gpio block r/w 01ff8834-35 gpiodir gpio block r/w 01ff8836-4f (not used) ?? 01ff8850-51 sstepclk scan/print motor control r/w 01ff8852-53 vpstepclk scan/print motor control r/w 01ff8854-5f (not used) ?? 01ff8860-6f (not used) ?? 01ff8870-71 rotnn bit rotation block r/w 01ff8872-73 brbwarp bit rotation block ? 01ff8874-75 rotlinelength bit rotation block r/w 01ff8876-8f (not used) ?? 01ff8880-1 125 sprescaler fax timing block r/w 01ff8882-3 iclkperiod fax timing block r/w 01ff8884-5 msintperiod fax timing block r/w 01ff8886-7 intclear fax timing block w 01ff8888-8f (not used) ?? 01ff8890-91 scancycle video/scan controller r/w 01ff8892-93 scanconfig video/scan controller r/w 01ff8894-95 scandotctrl video/scan controller r/w 01ff8896-97 scanlength video/scan controller r/w 01ff8898-99 scanstartdelay video/scan controller r/w 01ff889a-9b startedges video/scan controller r/w 01ff889c-9d startconfig video/scan controller r/w 01ff889e-9f clk2aedges video/scan controller r/w 01ff88a0-a1 clk2bedges video/scan controller r/w 01ff88a2-a3 clk2cedges video/scan controller r/w 01ff88a4-a5 adcsamplecfg video/scan controller r/w
MFC2000 multifunctional peripheral controller 2000 hardware description 4-18 conexant 100723a table 4-3. setup registers (2 of 2) address register name block name r, dr (dummy read), w, dw (dummy write) 01ff88a6-a7 clampctrl video/scan controller r/w 01ff88a8-a9 clampdelay video/scan controller r/w 01ff88aa-ab clampedges video/scan controller r/w 01ff88ac-ad led0edges video/scan controller r/w 01ff88ae-af led1edges video/scan controller r/w 01ff88b0-b1 led2edges video/scan controller r/w 01ff88b2-b3 led0pwm video/scan controller r/w 01ff88b4-b5 led1pwm video/scan controller r/w 01ff88b6-b7 led2pwm video/scan controller r/w 01ff88b8-b9 ledconfig video/scan controller r/w 01ff88ba-bb scaniaconfig video/scan controller r/w 01ff88bc-bd scanctrldelay video/scan controller r/w 01ff88be-bf adcconfig video/scan controller r/w 01ff88c0-c1 spiconfig video/scan controller r/w 01ff88c2-c3 spidata video/scan controller r/w (bit[15:8] ? r only) 01ff88c4-c5 (not used) ?? 01ff88c6-c7 vidlinecfg video/scan controller r/w 01ff88c8-c9 vidllstat video/scan controller r only 01ff88ca-cb vidoddflstat video/scan controller r only 01ff88cc-cd videvenflstat video/scan controller r only 01ff88ce-cf (not used) ?? 01ff88d0-df (not used) ?? 01ff88e0-ff reserved ?? 01ff88900-fff (not used) ? ?
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-19 4.2 cache memory controller 4.2.1 functional description 4.2.1.1 cache summary ? 4 kb instruction cache ram with expansion capability ? physical address cache access and cache tags ? two way set associative with lru algorithm ? 16 bytes cache line size with 128 cache lines in each way ? supports both arm and thumb mode instructions ? cache memory can be enabled or disabled ? provides lock function and flush function ? interfaces between arm7tdmi and siu (system interface unit) 4.2.1.2 cache overview the cache controller is an instruction only cache; a level 1 cache for arm7tdmi. the cache, when enabled, will support zero wait state sequential instruction access from arm provided the instruction is in the cache and valid (cache hit). if an instruction is not found in the cache memory (cache miss), the cache controller will activate the lru (least recently used) replacement algorithm. in this case, the arm will incur a number of wait states depending on the memory speed. the 4 kb cache memory is divided into two ways, which means 2 kb per way. each way is further divided into 128 cache lines with 16 bytes of instructions in each line. if a cache miss is detected and cache line fill is required, the cache controller will replace the least recently used (lru) cache line, the cache line fill operation is done in burst (sequential), minimizing the overhead. the ability for the software to lock the entire cache or individual line and to flush the entire cache memory contents are provided. in addition, the cache memory and cache tags can be placed in test mode for power-up verification and system diagnoses. the entire cache memory and cache controller can also be disabled allowing the arm to bypass the cache controller unit. cache ram ( 2k bytes ) cache tag (128 sets) a[31 : 11] v 21 bits 1 bit 32 bits 32 bits 32 bits 32 bits 16 bytes w0 w2 w1 w3 way 0 way 1 1 bit l r u 128 sets l 1 bit figure 4-3. MFC2000 cache organization
MFC2000 multifunctional peripheral controller 2000 hardware description 4-20 conexant 100723a table 4-4. cache tag data format (for test mode read/write operation) cache tag data format bits description 31 lru bit, accessible only through way 0 tag read 30:23 unused bits 22 lock 21 valid 20:0 a[31:11] 4.2.1.3 cache ram the cache ram consists of four 512 x 16 asynchronous static ram modules, and they are organized into two 512 words (32 bit/word) to support two way set associative. the memory map for direct accesses while in test mode or lock mode is as follows: way 0: $01fe0000-$01fe07ff way 1: $01fe0800-$01fe0fff 4.2.1.4 cache tags the cache tags are defined as follows: valid (1 bit): a 1 in this bit indicates that the tags and data at the addressed cache line are both valid. neither tags nor data have meaning if this bit is 0. upon power up, the tag memories will undergo an automatic flush operation that requires 128 clocks. during the flush operation, the cache is disabled. lock (1 bit): a 1 in this bit indicates that the tags and data at the addressed cache line are both valid and locked and should not be replaced when a cache miss is detected. lru (1 bit): indicates that the tags and data at the addressed cache line (if not locked) at way 0 can be replaced if this bit is 0. if this bit is a 1, the cache line and tags in way 1 should be chosen for replacement. unused (8 bits): unused bits are undefined. a[31:11]: address tag bits which together with cache address (a[10:4]), uniquely identify a cache line in the entire 32-bit physical address space. the cache tags are memory mapped to the following address space (not fully utilized) when in the test mode or lock mode : way 0: $01fe1000-$01fe17ff way 1: $01fe1800-$01fe1fff it should be noted that bits 2-3 of the addresses are not decoded during the tag entry accesses, i.e., $sa+00, $sa+04, $sa+08, and $sa+0c all access the same tag entry. 4.2.1.5 accessing the cache to access the cache during an instruction fetch, the cache controller performs the normal cache operation. if accesses are performed during test mode or lock mode, the tag ram and cache ram are treated as regular memories. if the cache is enabled, regardless of cache hit or miss, the cache controller asserts one wait state for every non-sequential cycle to start the instruction fetch cycle.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-21 if the access results in a hit, the wait state is de-asserted and a 32-bit cache data is output to the arm. subsequent sequential (s-cycles) access(es) require zero wait state if they are found in the same cache line. if the access crosses cache line boundary, the cache controller will add one wait state for the first s cycle that crosses the boundary, and then add additional wait states if it results in a cache miss. if the access misses the cache, the cache controller extends the wait states until the corresponding cache data or cache line is received from external memory through siu. the number of wait states inserted is affected by the status of the lock bit for the corresponding cache line. if the line is not locked, then the cache line fill operation will be performed and the required wait state will depend on the speed and the data width of the external devices. if the cache line is locked, the cache controller will re-generate the arm cycle and forward the cycle to siu. the required wait states in this case will be much less than that of cache line fill, but still a few cycles more than a simple pass-through operation when the cache is disabled. this is due to the time required for the tag comparison. it should be noted that, in the case of cache line fill, the requested data is not transferred to the arm until the cache line fill operation is completed. 4.2.1.6 definition of a cache hit there are two requirements for a cache hit. first the arm a[31:11] must match the cache address tags accessed by a[10 :4] in an instruction fetch cycle. second, the addressed cache line must be valid. 4.2.1.7 lru algorithm the lru (least recently used) algorithm is applied when a cache miss is detected. this algorithm first looks for a non-valid line in the set for a replacement. the order that is used for this checking is way 0 first, then way 1. if both lines associated with the set are valid, then the lock bit check is followed. if both are not locked, then the lru bit (one bit only) associated with the set is tested. if it is a zero, the cache line in way 0 is replaced; otherwise, way 1. if both are locked, no replacement can be performed and the cache controller will convert the cycle from instruction fetch to data fetch and forward the cycle to siu for the requested instruction. if only one of the two lines is locked, the unlocked line will be chosen for the replacement. 4.2.1.8 siu interface the arm to siu interface behaves differently depending on whether the cache is enabled or not. if the cache is disabled, the only affect that the cache controller adds to the arm/siu interface is a small propagation delay for those signals that pass through the cache controller (refer to the block diagram for the pass-through signals). on the other hand, if the cache is enabled, the cache controller will response to an instruction cycle by either providing data to the arm in a cache hit, or, converting the instruction cycle to a series of burst data cycle(s) and forwarding them to siu in a cache miss.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-22 conexant 100723a 4.2.2 register description name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default cache control register $01ff8800 n/a flush cache global lock lock mode test mode cache enable n/a n/a rst value 00h this register resides in the siu block. the siu, upon detecting the set condition for a given bit(s) in this register, asserts the corresponding control signal(s) to the cache controller. bit 7 reserved bit 6 flush cache read/writable bit. writing a 1 to this bit flushes all valid bits, lru bits, and lock bits in the cache tag to zero. it requires 128 cycles to flush the entire tag memory area. this bit will be automatically reset upon completion of the flush operation. flush does not reset global lock or cache enable condition if present. bit 5 global lock read writable bit. writing a 1 to this bit locks the entire cache memory; a 0 unlocks the cache. this bit provides a quick way to lock the entire cache memory. bit 4 lock mode read/writable bit. writing a 1 to this bit and a 0 to the cache enable bit places the cache in the lock mode. the cache stays in lock mode until a 0 is written to this bit. bit 3 test mode read/writable bit. writing a 1 to this bit and a 0 to the cache enable bit sets the cache into test mode. in test mode, the cache rams and tags can be accessed in the same manner as regular memory. certain tag bits are readable only. the cache stays in test mode until a 0 is written to this bit. bit 2 cache enable read/writable bit. writing a 1 enables the cache and the cache stays enabled until a 0 is written or a reset is received. power-up resets to 0 and disables the cache. bit 1 reserved bit 0 reserved
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-23 4.2.3 firmware operation 4.2.3.1 enabling the cache the cache enable bit in the siu cache control register determines if the cache is enabled or not. in power-up reset state, the cache is disabled. if disabled, all cpu accesses go directly to the siu and the cache controller passes through all signals from arm to siu. after the power-up reset, all cache tag entries are flushed after 128 clocks. if the cache is enabled after power-up, the cache controller starts to update the cache memory and cache tag after the flush operation is completed. 4.2.3.2 locking the cache the system can lock the entire cache memory by setting global lock bit to 1 in cache control register. the cache remains locked until the bit is reset. setting and resetting the global _lock bit has no effect on the individual lock bit set during the lock mode, the individual lock bit can be cleared by setting flush_cache bit to 1. the system can also lock an individual cache line by placing the cache in the lock mode. once in the lock mode, the system can access the cache ram and tag ram as if they were regular memory. a write to the tag entry sets both the lock bit and valid bit for the corresponding tag. the software is responsible for properly mapping the instructions from rom (?where to be cached in?) into cache ram and tag ram (?where to be locked down?) based on the modular of 2048 bytes. in other words, the a10-a2 of address lines used for the rom code and cache/tag ram?s entry must be identical, and the a31-a11used for the rom code becomes the data entry for the corresponding tag entry. caching is disabled during lock mode; the system must exit the lock mode before enabling the cache. once a cache line is locked, lru replacement policy prevents the replacement of the locked cache line. if both cache lines in a set (two ways) are locked, the lru algorithm is not able to replace either line; thus, no cache line fill is performed; instead, a data fetch n (non-sequential) cycle is generated by the cache controller and sent to the siu. a minimum of 5 wait states is expected. 4.2.3.3 flushing the cache the system can clear the cache by activating the flush input. this signal is generated by the siu when the flush bit in the cache control register is set by the system. upon receiving the flush input, the cache controller starts the flush operation. the operation takes 128 clocks to resets all the tag valid bits, lru bit, and lock bit. during the operation the cache, if enabled, is temporarily disabled until the flush is completed. the flush bit is cleared automatically at the end of the flush operation. 4.2.3.4 testing the cache and tag memories the system can access the cache memory and tag ram as regular memory does when in test mode. test mode is entered after setting the test bit in the cache control register. in test mode, the tag ram and cache ram behave like an ordinary memory for read/write cycles. this test feature is not only required for the power-up self test, but also is important for diagnostics when a system problem develops. the contents of the tag and cache ram are essential to the investigation of the problem. note : the valid bit, lock bit, and lru bit can only be read, not written, and lru is only available through way 0 access . note : it is important to flush the cache upon completion of the test mode.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-24 conexant 100723a 4.3 siu 4.3.1 functional description the system integration unit (siu) is responsible for interfacing between the arm7tdmi core, the cache memory controller, the internal peripheral bus (ipb), and the external bus (eb). the arm7tdmi core and the cache memory controller are on the internal system bus (isb). the isb data bus is 32-bits wide and the ipb and eb data buses are 16-bits wide. the siu generates the external chip selects along with chip selects to all the internal peripherals. it provides the following functions: 1. interfaces between the internal peripheral bus (ipb), the internal system bus (isb) and the external bus (eb). the siu allows bus master devices on the ipb and isb. 2. control the chip selects to devices on the ipb, the isb, and the eb. 3. address multiplexing for dram access. 4. rom interleave control (including wait state control for the interleave mode): no interleave and 2-way interleave with external q-switch. 5. fast page mode rom operation. 6. even though arm7tdmi is fixed to the little endian in this MFC2000 chip, the siu can support the little endian or big endian for the dma operation. 7. support arm and thumb mode operations. 4.3.1.1 ipb, isb and external bus ipb bus the ipb bus supports both 8-bit and 16-bit peripherals. the arm or an internal bus master such as dma can access a device residing on the ipb bus. the siu provides the chip selects to each of the internal peripheral devices. the chip selects are driven in the second clock cycle of an ipb bus cycle. the peripheral device needs to decode only the address lines required to access the specific registers within the block. transactions on the ipb bus only occur when a device on the ipb bus is being accessed. all accesses on the ipb bus require two peripheral bus clock cycles (2 siuclk?s). during the first cycle, the address is decoded and determined if an access to an internal peripheral is occurring. during the second cycle the peripheral chip select is asserted, and the access occurs. during write operations to peripherals, signals bs[1:0] are used to signal which bytes are valid on the data bus. 8-bit peripherals can ignored these signals. 16-bit peripherals must use these signals to allow each 8-bit half of the peripheral registers to be written independently. this is due to the fact that the arm compiler may generate two byte transactions when accessing a 16-bite register on the ipb instead of a single halfword transaction. during read operations, the peripherals must fill the 16-bit ipb data bus. if the peripheral is less than 16-bit wide, it should fill the empty bits with 0.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-25 isb bus the isb bus is used for connecting arm and cache controller to the highest performance. the 32-bit isb bus directly interfaces with the arm core 32-bit data bus. the cache memory controller resides on this bus. all control signals to and from the arm, and its address bus go through the cache memory controller regardless of the cache enable bit. the cache controller control register resides in the siu. when the arm is fetching instructions, and it is a cache hit situation, the arm gets the instructions from the cache. the siu lets the other bus masters have the bus. when the arm is fetching instructions, and it is a cache miss situation, the siu must perform a burst read of eight halfwords (4 words) to fill up the cache line if the cache line is not locked. if the cache line is locked, then the siu reads in two halfwords (one word) of instruction. when the arm is fetching data, data is passed directly from the siu to the arm. eb bus the eb bus is used for connecting external memories and devices. the width of the selected slave device is programmable in the chip select configuration register. the external a[23:12] and a[11:0] addresses are multiplexed through a[11:0] pins. the ale signal is provided to latch a[23:12] addresses externally. external chip selects the siu provides programmable external chip selects. each chip select is programmable through the chip select configuration register. ? each chip select can be configured to be: ? enabled or disabled (default = enabled). ? programmable from 0 up to 7 wait states. ? programmable read/write delay-on (write strobe activated one or two siuclk cycles later). ? programmable write early-off (read or write strobe deactivated one siuclk cycle earlier). ? programmable to allow for 8 or 16 bit devices. the siu will automatically perform the necessary transaction to access any size data as long as the source of the transaction is internal. note: the rd/wr-delay-on and wr-early-off settings should be disabled for zero wait state access. for other wait state settings (> 1wait state), the delay-on and early-off will shorten the width of read/write strobe. firmware has the responsibility to set rd/wr-delay-on and wr- early-off bits correctly. otherwise, read or write strobes may disappear. for example, if 1 wait state and 1 rd/wr-delay-on are set for a chip select, the read strobe is not suppressed when firmware tries to do a read operation. if 2 wait states, 1 wr-early-off and 1 rd/wr-delay-on are set for a chip select, the write strobe is not suppressed when firmware try to do a write operation. rom interface the siu supports non-interleave, 2-way interleave and fast page mode access to rom, depending on the rom access configuration pins (ae[2]/rom_cfg[0] and ao[2]/rom_cfg[1] pins). following are the four configurations supported by the siu. rom access configuration[1:0] rom mode 00 8-bit non-interleave 01 16-bit non-interleave 10 16-bit 2-way interleave 11 16-bit fast page mode
MFC2000 multifunctional peripheral controller 2000 hardware description 4-26 conexant 100723a the MFC2000 assigns 4 multi-function pins (ae[2], ao[2], ae[3], and ao[3]) to facilitate the interleave access. siu generates 4 signals on these 4 pins to control roms for the following types of interleave accesses. ? in 2-way interleave mode, MFC2000 pins ae[2] ,ao[2], ae[3], and ao[3] are connected to pin a[1:0] of the even and odd external roms. MFC2000 pins a[1:0] are used to enable the rom?s data busses. romcsn cs oe d a23 a2 a1 a0 d even dd a23 a2 a1 a0 cs oe d odd a[25] a[25] a[4] a[4] ae[3] ao[3] ae[2] ao[2] en en q-sw q-sw a[1] a[0] rdn figure 4-4. 2-way interleave rom connection ? the romcsn can be programmed to have up to 7 wait states for the initial access, and up to 1 wait state for the sub-sequential access. ? the write access to the rom chip select area (romcsn) is allowed. it is customer?s choice to use it or not. ? to use nor-type flash memory in the rom chip select area, wren and wron are designed to be used as the write strobes for the different banks in the interleave mode (not for the higher and lower bytes). therefore, the 16-bit wide flash memory should be used in order to avoid the extra glue logic. ? for non-interleave mode flash memory in the rom chip select area, the wron is used to access the higher byte of the 16-bit data bus and the wren is used to access the lower byte of the 16-bit data bus. assume that w wait states are needed for the initial access to rom and s wait states (s = 0 or 1) for the sub- sequential access according to the cpu clock frequency and the rom speed. for a burst of 8 half-words interleave access, the wait state of each half-word access, assuming the starting address?s a[3:1]=000. we can have the following table show all different access modes for reading from rom.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-27 table 4-5. access modes for reading rom rom access mode data type cache memory wait states notes 8-bit non- interleave instruction cache enabled and cache miss w,w,w,w,w,w,w,w w,w,w,w,w,w,w,w (16 sequential accesses) this is cache burst access. save the address decoding cycle for all accesses except the first access. 16-bit non- interleave instruction cache enabled and cache miss w,w,w,w,w,w,w,w (8 sequential accesses) this is cache burst access. save the address decoding cycle for all accesses except the first access. 8-bit non- interleave instruction cache disabled w if the sequential access occurs, save the address decoding cycle for all accesses except the first access. 16-bit non- interleave instruction cache disabled w if the sequential access occurs, save the address decoding cycle for all accesses except the first access. 8-bit non- interleave data not applied w if the sequential access occurs, save the address decoding cycle for all accesses except the first access. 16-bit non- interleave data not applied w if the sequential access occurs, save the address decoding cycle for all accesses except the first access. 16-bit 2-way interleave instruction cache enabled and cache miss w, s, w-s-1, s, w-s-1, s, w-s-1, s (8 sequential accesses) this is cache burst access. 0 or 1 wait state is programmable and depends on the cpu clock frequency and the rom speed. if ?w-s-1? is less than 1, it will be forced to 1. 16-bit 2-way interleave instruction cache disabled w, s, w-s-1, s, w-s-1, s, w-s-1, s (one interleave access sequence) the actual sequential access length is dynamic. 0 or 1 wait state is programmable and depends on the cpu clock frequency and the rom speed. if the starting address of the sequential access is not lined up with the octal address boundary of the interleave access, the partial interleave access sequence should be done. then, restart the interleave access sequence at the octal address boundary of the interleave access. even if the stopping address of the sequential access is not lined up with the octal address boundary of the interleave access, the access sequence must be stopped immediately at anywhere. if ?w- s-1? is less than s, it will be forced to s. 16-bit 2-way interleave data cache enabled and cache miss w, s, w-s-1, s, w-s-1, s, w-s-1, s (one interleave access sequence) the actual sequential access length is dynamic. 0 or 1 wait state is programmable and depends on the cpu clock frequency and the rom speed. if the starting address of the sequential access is not lined up with the octal address boundary of the interleave access, the partial interleave access sequence should be done. then, restart the interleave access sequence at the octal address boundary of the interleave access. even if the stopping address of the sequential access is not lined up with the address boundary of the interleave access, the access sequence must be stopped immediately at anywhere. if ?w- s-1? is less than s, it will be forced to s.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-28 conexant 100723a if the rom write access (flash memory in the rom address range) is performed in the interleave access mode, the siu still generates those signals to control roms and external multiplexes to perform the interleave access. but, all the access (no matter if it is the sequential access or not) have w wait states. external dram interface when the decoded address from any bus master matches external dram address, the siu will issue a dram request to the dram controller and start the transaction . first, it routes the dram row address to the address bus. after receiving the column enable signal from the dram controller, the siu multiplexes the dram column address to the same address bus according to the size of the dram . the siu will perform the next transaction after receiving the dram ready back from the dram controller signaling the dram transaction is complete. the siu also looks at the burst request signals from the bus master who owns the bus to generate the burst signal to the dram controller indicating a burst access. bus arbitration the bus arbitrator block arbitrates control of the internal and external busses between the arm7tdmi core and any bus master devices (such as dma) residing on the ipb or isb. the arm core is the default bus master and has control of the bus whenever no other bus master requests it . in arbitrating control of the bus, the arbitrator gives highest priority to the dma controller and then, the arm core. in burst mode access (both dma and cpu), the bus is not arbitrated within the burst access. in order to prevent a bus master from hogging the bus. the maximum burst length allowed is eight halfword access. the dma of internal peripherals only bursts a maximum of five halfwords. a bus master requests the bus by asserting request. the arbitrator grants the bus to the requesting bus master by asserting grant. the requesting bus master must continue to assert request for as long a bus ownership is required and release the bus by de-asserting request. the arbitrator always inserts a single dead cycle before granting the bus to another bus master. little endian and big endian the little endian and big endian control is only for internal dma (the dma request is from an internal peripheral). when a dma access requires different endian format. the corresponding bit of the dmaendian register needs to be set. the siu will transform the endian format; from little endian dma address and data into big endian format or from big endian dma address and data into little endian format. the even and odd write signals (wren, wron) also change accordingly. the following tables show the final addresses and data at the asic pins, and the resulting dma read or write data. internal dma data size is always 16 bits (a halfword).
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-29 table 4-6. read operation (internal peripheral gets data from memory) big endian little endian dma size mem size dma_ad dma data (output) mem addr mem data (input) half word byte 0000 byte 2, byte 3 0011,0010 byte 3, byte 2 half word byte 0010 byte 0, byte 1 0001,0000 byte 1, byte 0 half word half word 0000 byte 2, byte 3 0010 byte 3, byte 2 half word half word 0010 byte 0, byte 1 0000 byte 1, byte 0 table 4-7. write operation (internal peripheral puts data into memory) little endian big endian dma size mem size dma_ad dma data (input) mem addr mem data (output) wron wren half word byte 0000 b1,b0 0011,0010 b0,b1 0 0 half word byte 0010 b3,b2 0001,0000 b2,b3 0 0 half word half word 0000 b1,b0 0010 b0,b1 0 0 half word half word 0010 b3,b2 0000 b2,b3 0 0
MFC2000 multifunctional peripheral controller 2000 hardware description 4-30 conexant 100723a 4.3.2 register description siu control address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default siu configuration (siuconfig) 01ff8801 (not used) (not used) (not used) (not used) (not used) (not used) (not used) cs4n read only rst. value xxxxxxx0b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default siu configuration (siuconfig) 01ff8800 cs3n write only flush cache global lock cache lock mode cache test mode cache enable disable force external disable abort rst. value 00h read value 00h bit 8 cs4n read only writing a 1 makes cs4n a read only cs. default is 0. bit 7 cs3n write only writing a 1 makes cs3n a write only cs. default is 0. bit 6 flush: write only bit. writing a 1 generates a pulse which flushes all valid bits, lru bits and lock bits in the cache tag. default is 0 bit 5 global_lock: read/writable bit writing a 1 locks the whole cache. the cache stays in lock mode until a 0 is written. default is 0. bit 4 cache_lock: read/writable bit writing a 1 places the cache in the lock mode and the cache stays in lock mode until a 0 is written. each cache line is locked individually . default is 0 bit 3 cache_test: read/writable bit writing a 1 sets the cache into test mode and the cache ram and tags can be accesses as regular memory. note that certain tag bit only readable . the cache stays in test mode until a 0 is written to this bit. default is 0. bit 2 cache_enable: read/writable bit writing a 1 enables the cache and the cache stays enabled until a 0 is written or a reset is received. power-up resets to 0, so the cache is disabled. bit 1 force_external this signal will disable the forcing of all accesses to be visible on the external bus regardless of destination. if this signal is enabled, only external transactions will be visible on the external bus. 1 is disabled, 0 is enabled. default is 0. bit 0 disable_abort: this signal disables abort generation for internal and external access. if this signal is a 1, all transactions to internal and external address space will be allowed to occur regardless of if an valid internal or external peripheral exists. if this signal is 0, then accesses must be to valid peripheral locations or an abort signal will be generated. default is 0.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-31 external chip select control registers associated with each external chip select pin is a register to control automatic functions that will be executed when a location within the chip select range is accessed. all bits default to 0 unless otherwise specified. several control functions are common between the various chip select register. a chip select is enable when the enable bit is set to 1. wait states defines the number of wait states that are added to the associated bus cycle, in increments of siuclk cycle. a bus cycle is 1 siuclk. size is the width of the external devices peripherals using the chip select. the allowable widths are 8 and 16 bits. size are coded : 0=byte, 1 = half-word. if the size of the data is larger than the size of the peripheral, the siu will automatically perform multiples accesses to complete the transaction. default to 0. where applicable, strobe delay on = 1 delays the activation of rdn or wrn by 1 clk. write early off deactivates the wrn strobe by 1 clk earlier. address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default romcs control (romctrl) 01ff8803 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default romcs control (romctrl) 01ff8802 read/write strobe delay on mode[1] (read only) mode[0] (read only) subsequent wait wait[2] wait[1] wait[0] enable rst. value 1??11111b read value 1??11111b bit 7 read/write strobe delay on (default = 1) bits 6-5 mode[1:0] rom interface mode (read only). these 2 bits are read in directly from 2 pins (the ae[2]/rom_cfg[0] pin and the ao[2]/rom_cfg[1] pin during reset). 00: 8-bit non interleave 01: 16-bit non interleave 10: 16-bit 2way interleave 11: 16-bit fast page mode bit 4 subsequent access wait states in interleave mode (default = 1) bits 3-1 wait states or initial access wait states in interleave mode (default = 7) bit 0 romcsn enable. (default = 1) note: these controls are also applicable to the optional cs5n.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-32 conexant 100723a address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default cs5 control (cs5ctrl) 01ff8805 write strobe early off read/write strobe delay on[1] read/write strobe delay on[0] size wait[2] wait[1] wait[0] enable rst. value xxh read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default cs0 control (cs0ctrl) 01ff8804 write strobe early off read/write strobe delay on (not used) size wait[2] wait[1] wait[0] 0 rst. value 00x00000b read value 00h bit 7,15 write strobe early off (default =0) bit 6,14-13 read/write strobe delay on (default = 0) bit 5 (not used) bit 4,12 size (default = 0 . byte ) mode = 0: 8-bit access 1: 16-bit access bit 3-1, 11-9 wait states (default =0) bit 8 cs5n enable note: the enable control for cs0 is set by the battery control logic. address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default cs2 control (cs2ctrl) 01ff8807 write strobe early off read/write strobe delay on[1] read/write strobe delay on[0] size wait[2] wait[1] wait[0] enable rst. value 01h read value 01h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default cs1 control (cs1ctrl) 01ff8806 write strobe early off read/write strobe delay on[1] read/write strobe delay on[0] size wait[2] wait[1] wait[0] enable rst. value 01h read value 01h bit 15 write early off strobe (default =0 ) bit[14:13] read/write strobe delay on (default = 00) bit 12 size (default = 0. byte ) 0: 8-bit access 1: 16-bit access bit[11:9] wait states (default =0) bit 8 cs2n enable (default = 1) . bit 7 write early off strobe (default =0) bit[6:5] read/write strobe delay on (default = 00)
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-33 bit 4 size (default = 0. byte) 0: 8-bit access 1: 16-bit access bit[3:1] wait states (default =0) bit 0 cs1n enable (default = 1) address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default cs4 control (cs4ctrl) 01ff880f write strobe early off read/write strobe delay on[1] read/write strobe delay on[0] size wait[2] wait[1] wait[0] enable rst. value 01h read value 01h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default cs3 control (cs3ctrl) 01ff880e write strobe early off read/write strobe delay on[1] read/write strobe delay on[0] size wait[2] wait[1] wait[0] enable rst. value 01h read value 01h bit 15 write early off strobe (default =0 ) bit[14:13] read/write strobe delay on (default = 00) bit 12 size (default = 0. byte) 0: 8-bit access 1: 16-bit access bit[11:9] wait states (default =0) bit 8 cs4n enable (default = 1) bit 7 write early off strobe (default =0) bit[6:5] read/write strobe delay on (default = 00) bit 4 size (default = 0. byte) 0: 8-bit access 1: 16-bit access bit[3:1] wait states (default =0) bit 0 cs3n enable (default = 1) address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default modem cs control (mcsctrl) 01ff8809 (not used) (not used) (not used) (not used) (not used) (not used) (not used) modem interrupt select rst. value xxxxxxx0b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default modem cs control (mcsctrl) 01ff8808 write strobe early off read/write strobe delay on (not used) size wait[2] wait[1] wait[0] enable rst. value 00x00001b read value 01h bit 7 select p80 or external mirqn interrupt ( default =0, select p80 ) bit 7 write early off strobe (default =0 ) bit 6 read/write strobe delay on (default = 00) bit 5 (not used)
MFC2000 multifunctional peripheral controller 2000 hardware description 4-34 conexant 100723a bit 4 size (default = 0 . byte) 0: 8-bit access 1: 16-bit access bit 3,2&1 wait states (default =0) bit 0 mcsn enable. (default = 1) address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: flash memory control (flashctrl) 01ff880b (not used) (not used) (not used) (not used) (not used) fcs1n value for nand type fcs0n value for nand type fcs1n disable rst. value x8h read value 08h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: flash memory control (flashctrl) 01ff880a write strobe early off fcsn nand-type (not used) size wait[2] wait[1] wait[0] fcs0n disable rst. value 00x00000b read value 00h bit 10 output value of fcs1n when nand-type memory is used. not applicable for nor-type memory. bit 9 output value of fcs0n when nand-type memory is used. not applicable for nor-type memory. bit 8 1= disable fcs1n (default = 0: enable) when this bit is set to 1, pin pwm2/fcs1n is used as pwm2. bit 7 write early off strobe (default =0) bit 6 nand-type memory is used when this bit is set to 1. (default =0 . nor type). bit 4 size (default = 0 . byte) 0: 8-bit access 1: 16-bit access bit[3:1] wait states (default =0) bit 0 1= disable fcs0n (default = 0: enable) when this bit is set to 1, pin pwm0/fcs0n is used as pwm0.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-35 address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default rotpacked data register access control (rotpackctrl) 01ff880d (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default rotpacked data register access control (rotpackctrl) 01ff880c write strobe early off read/write strobe delay on[1] read/write strobe delay on[0] size wait[2] wait[1] wait[0] enable rst. value 01h read value 01h bit 7 write early off strobe (default =0 ) bit[6:5] read/write strobe delay on (default = 00) bit 4 size (default = 0. byte) 0: 8-bit access 1: 16-bit access bit[3:1] wait states (default =0) bit 0 rotpackeddata register access enable. (default = 1) note : this register is used to set up the access timing for the dma read from rotpackeddata register to the external pif device. it provides the control of wait states and rdn width when accessing the rotpackeddata.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-36 conexant 100723a 4.3.3 timing siuclk arm_a[31:0] a b c internal internal d a[11:0] a[11:0]+2 b[11:0] b[11:0]+1 b[11:0]+2 b[11:0]+3 c c[11:0] d[11:0] "+1 ext_ad[11:0] csn rdn wrn read data write data byte0 b1 b2 b3 ale a[23:12] b[23:12] c[23:12] d[23:12] (internal clock) figure 4-5. zero wait state, single access, normal read, normal write
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-37 (internal clock) siuclk arm_a[31:0] a bc internal a[11:0] a[11:0]+2 b[11:0] b[11:0]+1 b[11:0]+2 ext_ad[11:0] csn rdn wrn read data write data b[11:0]+3 byte0 byte1 byte2 byte3 ale a[23:12] b[23:12] c[23:12] figure 4-6. one wait state, single access, one read, one write
MFC2000 multifunctional peripheral controller 2000 hardware description 4-38 conexant 100723a (internal clock) siuclk arm_a[31:0] abc a[11:0] a[11:0]+2 b[11:0] b[11:0]+2 ext_ad[11:0] cs1n rdn wrn read data write data c[11:0] byte0 byte1 cs2n ale a[23:12] b[23:12] c[23:12] figure 4-7. two wait states, single access, read on delayed (cs1n), write early off (cs2n)
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-39 (internal clock) siuclk arm_a[31:0] ext_ad[11:0] csn rdn wrn read data write data a1 a2 a3 a4 a5 a6 a7 a8 a1[11:0] a2[11:0] a3[11:0] a4[11:0] a5[11:0] a6[11:0] a7[11:0] a8[11:0] octal boundary ale a1[23:12] a6[23:12] figure 4-8. zero wait state, burst access, normal read, normal write
MFC2000 multifunctional peripheral controller 2000 hardware description 4-40 conexant 100723a (internal clock) siuclk arm_a[31:0] a a+4 c ext_ad[11:0] romcsn wren/wron rdn b b+2 b+4 b+6 ale a[23:12] a[11:0] a[11:0]+4 b[23:12] b[11:0] b[11:0]+2 b[11:0]+4 b[11:0]+6 a[11:0]+2 a+2 figure 4-9. fast page mode rom access ? ? ? ? 1,0,0 read access followed by 1,1,1,1, write access
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-41 detail external bus timing siuclk (internal clock) rdn t ald d[15:0] (read) a[11:0] ext. cs's (romcsn, gpio21(mcsn),gpio7- 4(cs5,2n), cs1n,cs0n) t csd t rd t rd 3 wait states gpio[5] (cs3n), gpio[6] (cs4n) t cgd t dih t dis d[15:0] (write) t dod t doh wren, wron t wd t wd t wd t wd ale t ad t aah t aad upper address lower address figure 4-10. system bus timing ? ? ? ? read/write with wait states
MFC2000 multifunctional peripheral controller 2000 hardware description 4-42 conexant 100723a siuclk (internal clock) rdn d[15:0] (read) a[11:0] ext. cs's t csd t r0d t r0d wren, wron t w0d t w0d zero wait state gpio[5] (cs3n), gpio[6] (cs4n) t cg0d d[15:0] (write) t do0d t do0h t ad t di0h t di0s t as t ah t dh upper address lower address figure 4-11. system bus timing ? ? ? ? zero-wait-state read/write
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-43 siuclk (internal clock) rdn d[15:0] (read) a[11:0] romcs, cs5n t csd t rd 4 wait states (w=4) t dih t dis s= 1 2 wait states s= 1 t ad ae[2] ae[3] ao[2] ao[3] t iad t iad t iad t iad figure 4-12. system bus timing ? ? ? ? 2-way interleave read timing (s = 1)
MFC2000 multifunctional peripheral controller 2000 hardware description 4-44 conexant 100723a siuclk (internal clock) wren, wron d[15:0] (write) a[11:0] romcs, cs5n t csd t wd t wd 3 wait states (w=3) t dos 3 wait states 3 wait states t ad ae[2] ae[3] ao[2] ao[3] t iad t iad 3 wait states t doh t iad figure 4-13. system bus timing ? ? ? ? 2-way interleave write timing (s = 0 or 1)
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-45 table 4-8. read/write with wait states timing parameters parameter symbol min. max. units address delay time t ad 5 20 ns chip select delay time t csd - 20 ns read delay time for the normal case and delay-on) t rd 5 18 ns write delay time (the normal case, delay-on, and early-off) t wd 5 12 ns cs[4:3] delay time (gated with read or write strobe) t cgd - 18 ns data input setup time t dis 8 - ns data input hold time t dih 0 - ns data output delay time t dod - 21 ns data output hold time t doh 5 21 ns read delay time (for zero wait state) t r0d 5 11 ns write delay time (for zero wait state) t w0d 5 11 ns cs[4:3] delay time (gated with read or write strobe for zero wait state) t cg0d - 20 ns data input setup time (for zero wait state) t di0s 8 - ns data input hold time (for zero wait state) t di0h 0 - ns data output delay time (for zero wait state) t do0d - 21 ns data output hold time (for zero wait state) t do0h - 21 ns 2-way interleave address delay time t iad - 11 ns ale address setup time t aad 10 ns ale address hold time t aah 2 ns ale delay time t iald - 10 ns address setup time (read and write) t ias 3 - ns address hold time (read and write) t iah 2 - ns data hold time (write) t idh 2 - ns note : siuclk is the internal system interface clock. these values are for siuclk = 30 mhz. when s=0 in the 2-way interleave read operation, t iad parameter is still same. 4.3.4 firmware operation caution only word or half-word accesses that happen on their respective boundaries are valid. if the access is to a non-boundary address, the siu ignores the last 2 lsbs (word access) or 1 lsb (half word access) and reset the address to the appropriate boundaries. for 16-bit register, writing a byte to the even address (register address) will update the lower 8-bits of the register. writing a byte to the odd address (register address + 1) will update the upper 8 bits of the register. bs[1:0] indicate which byte is written. writing a halfword to either the even or odd address will update all 16-bits.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-46 conexant 100723a 4.4 interrupt controller 4.4.1 function description table 4-9. MFC2000 interrupt and reset signals description external source internal source irq number modem interrupt mirqn p80 core irq0 countach bus system interrupt (irqcbs) countach imaging dsp bus system irq1 print subsystem interrupt prtirqn ? irq2 scan step interrupt (irqsstep) motor control block irq3 vertical print step interrupt (irqvpstep) motor control block irq4 sasif interrupt (irqsasif) ? sasif block irq5 dma ch.2 interrupt (irqdma2) ? dma control block irq6 bi-level resolution conversion interrupt (irqbrc) ? bi-level resolution conversion block irq7 dma ch.10 interrupt (irqdma10) ? dma control block irq8 reset batrstn resetn watchdog timer & power-down lockout n/a vsc if interrupt (irqvsc) ? vsc if block irq9 timer interrupt 1 (irqtimer1) ? interrupt controller irq10 external interrupt 1 irq11 ? irq11 pio interrupt (irqpio) ? pio block irq12 external interrupt 2 irq13 ? irq13 t.4/t.6 interrupt (irqt4) ? t.4/t.6 block irq14 sopif interrupt (irqsopif) ? sopif block irq15 system interrupt (irqsys) irq16 power down block irq16 software interrupt (irqsw) ? interrupt controller irq17 ssif interrupt (irqssif) ? ssif irq18 dma ch.5 interrupt (irqdma5) ? dma controller irq19 smartdaa if interrupt (irqsdaa) ? smartdaa if irq20 timer interrupt 2 (irqtimer2) ? interrupt controller irq21 usb interrupt (irqusb) ? usb block irq22
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-47 this section describes the three methods of interrupting the cpu program flow, which are: ? reset ? interrupts for the normal functions (irqs) ? interrupt for the development system (through the irq16 pin)/power down (through the power down block) the reset signal is controlled by the prime power reset block. irqs and sysirqn are managed by the interrupt controller and are sent to the arm as either an irq or a fiq if enabled. table 4-9 summarizes the interrupts and their sources. 4.4.1.1 reset an active level on the cpu reset input halts program execution and resets the cpu's internal registers. when the cpu's reset input is released, the cpu begins program execution at the address located in the reset vector. this signal can be activated externally by putting low levels on the batrstn or resetn pins, or internally by the watchdog timer or the battery power control logic lockout circuitry. (for more information, see section 5-1.) 4.4.1.2 system interrupt the system interrupt can be activated externally by the programmable interrupt irq16 or by the power down signal from the power down block. this interrupt is treated the same as other interrupts in the interrupt controller. firmware has the responsibility to make it the highest priority and to use it as the nmi function which is provided by many other cpus. the input from the power down block is detected and or?ed with the programmable external irq16 pin. this combined signal is then synchronized to the rising edge of siuclk, and then clocked to the falling edge of siuclk before an interrupt will be operated in the interrupt controller. for normal system operation, the system interrupt represents a loss of system power, indicated by power down signal going low. the system interrupt control firmware performs the necessary power-down maintenance operations, and then writes to the lockout enable register (lockenn) to protect the battery backed-up registers during loss of power. (note that activating lockout also generates a reset). 4.4.1.3 interrupts for normal functions the level-mode interrupt is provided for internal and external interrupts. all internal interrupts are high-level interrupts. the external modem interrupt is a low-level interrupt. all other external interrupts are programmable to be either high/low/level/edge interrupts. there are only two kinds of registers needed for the interrupt controller; one is the interrupt enable register and another is the interrupt event register. the interrupt controller does not prioritize the multiple sources of interrupts and does not generate the interrupt addresses. it only provides interrupt masking for all of interrupts including the system interrupt (i.e., enable/disable control), and generates the interrupt request for the cpu. when the bit corresponding to an interrupt in the interrupt enable register is set, it enables the interrupt request to cause an interrupt. when the bit is cleared, it masks the interrupt. when the event corresponding to an interrupt bit in the interrupt event register occurs, this bit needs to be set on the rising edge of siuclk whether it is enabled or not. on the falling edge of siuclk, the interrupt controller generates the interrupt (irqn and fiqn) to cpu. this interrupt controller has two identical sets of interrupt logic and registers for irqn and fiqn. firmware needs to decide which interrupts trigger irqn and which interrupts trigger fiqn. in the interrupt subroutine, the cpu needs to clear the interrupt event from the interrupt source. then, this bit will be reset at the following rising edge of siuclk. for the software interrupt, the interrupt source is the interrupt bit in the interrupt event register itself. therefore, the cpu needs to write a 1 to generate the software interrupt and write a 0 to clear the software interrupt. the source of the irq is required to latch the interrupt signal and hold the signal active until the cpu processes the irq. the cpu firmware clears the source of the irq before exiting the irq's service routine. if any irq's are pending when new irq's are enabled by either setting the interrupt enable registers or the interrupt disable bit in the cpu processor status register, the enabled irq causes an almost immediate cpu interrupt [the cpu only acknowledges interrupts during the op code fetch of an instruction].
MFC2000 multifunctional peripheral controller 2000 hardware description 4-48 conexant 100723a external interrupts the optional irq13 and irq11 external interrupt requests share pins with gpio9 and gpio8, respectively, and these interrupts are enabled by setting the corresponding bits in the irq enable registers to 1. these interrupt enable bits must be set to 0 when using gpio[9:8] as gpio to prevent these pins from causing interrupts. if an external interrupt source is connected to gpio8 and/or gpio9, the corresponding gpio direction control register must remain set to 0 (gpi) [default] to avoid bi-directional conflicts with the gpio output. dedicated external interrupt pins are provided for an active low modem interrupt (mirqn). all other external interrupts (irq2, irq11, irq13, and irq16) are programmable to be either active low or high, edge or level triggered. all external interrupts are resynchronized in the asic. internal interrupts internal interrupts are provided for the countach imaging dsp bus system (irqcbs), the t.4/t.6 logic (irqt4), the vertical printer stepper motor (irqvpstep), the scan stepper motor (irqsstep), the parallel io block (irqpio), usb interface (irqusb), the 50ms timer1 and timer2 (irqtimer1, irqtimer2), dma channel 2 (irqdma2), bi-level resolution conversion (irqbrc), dma channel 10 (irqdma10), scanner if (irqvsc), sopif (irqsopif ), sasif (irqsasif), software interrupt (irqsw), ssif (irqssif), dma channel 5 interrupt (irqdma5), and the sdaa interface interrupt (irqsdaa).
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-49 4.4.2 register description 4.4.2.1 irq/fiq event1 register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: irqfiqevent1 0x01ff8021 irq15 irqsopif event status irq14 irqt4 event status irq13 irqext2 event status irq12 irqpio event status irq11 irqext1 event status irq10 irqtimer1 event status irq9 irqvsc event status irq8 irqdma10 event status rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: irqfiqevent1 0x01ff8020 irq7 irqbrc event status irq6 irqdma2 event status irq5 irqsasif event status irq4 irqvpstep event status irq3 irqsstep event status irq2 irqprt event status irq1 irqcbs event status irq0 mirq event status rst value 00h read value 00h bit 15 internal interrupt from sopif block. read only. bit 14 internal interrupt from t4/t6 block. read only. bit 13 external interrupt 2. programmable. read only. bit 12 internal pio interrupt from pio block. read only. bit 11 external interrupt 1. programmable. read only. bit 10 internal timer 1 interrupt up to 50 ms. read only. bit 9 internal video scan controller interrupt from vsc if block. read only. bit 8 internal dma channel 10 interrupt from dma controller block. read only. bit 7 internal bi-level resolution conversion interrupt from blrc block. read only. bit 6 internal dma channel 2 interrupt from dma controller block. read only. bit 5 internal sasif interrupt from sasif block. read only. bit 4 internal vertical print step interrupt from motor control block. read only. bit 3 internal scan step interrupt from motor control block. read only. bit 2 external print subsystem interrupt. programmable. read only. bit 1 internal countach bus system interrupt from countach bus system. read only. bit 0 external modem interrupt (active low) or the internal p80 core interrupt. read only.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-50 conexant 100723a 4.4.2.2 irq/fiq event2 register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: irqfiqevent2 0x01ff8023 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: irqfiqevent2 0x01ff8022 (not used) irq22 irqusb event status irq21 irqtimer2 event status irq20 irqsdaa event status irq19 irqdma5 event status irq18 irqssif event status irq17 irqsw event status irq16 irqsys event status rst value x0000000b read value 00h bit 6 internal usb interrupt from usb block. read only. bit 5 internal timer 2 interrupt up to 50 ms. read only. bit 4 internal smartdaa interface interrupt from smartdaa if block. read only. bit 3 internal dma channel 5 interrupt from dma controller block. read only. bit 2 internal ssif from ssif block. read only. bit 1 internal software interrupt. when cpu writes a 1, the software interrupt is issued. when cpu writes a 0, the software interrupt is cleared. r/w. bit 0 internal system interrupt from programmable external interrupt 16 or power down circuit read only. 4.4.2.3 irq enable1 register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: irqenable1 0x01ff8025 enable irq15 irqsopif enable irq14 irqt4 enable irq13 irqext2 enable irq12 irqpio enable irq11 irqext1 enable irq10 irqtimer1 enable irq9 irqvsc enable irq8 irqdma10 rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: irqenable1 0x01ff8024 enable irq7 irqbrc enable irq6 irqdma2 enable irq5 irqsasif enable irq4 irqvpstep enable irq3 irqsstep enable irq2 irqprt enable irq1 irqcbs enable irq0 mirq rst value 00h read value 00h bit 15 ? 0: when 1 will enable the corresponding interrupt and when 0 will mask that interrupt out. r/w.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-51 4.4.2.4 irq enable2 register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: irqenable2 0x01ff8027 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: irqenable2 0x01ff8026 (not used) enable irq22 irqusb enable irq21 irqtimer2 enable irq20 irqsdaa enable irq19 irqdma5 enable irq18 irqssif enable irq17 irqsw enable irq16 irqsys rst value x0000000b read value 00h bit 3 ? 0: when 1 will enable the corresponding interrupt and when 0 will mask that interrupt out. r/w. 4.4.2.5 fiq enable1 register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: fiqenable1 0x01ff8029 enable irq15 irqsopif enable irq14 irqt4 enable irq13 irqext2 enable irq12 irqpio enable irq11 irqext1 enable irq10 irqtimer1 enable irq9 irqvsc enable irq8 irqdma10 rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: fiqenable1 0x01ff8028 enable irq7 irqbrc enable irq6 irqdma2 enable irq5 irqsasif enable irq4 irqvpstep enable irq3 irqsstep enable irq2 irqprt enable irq1 irqcss enable irq0 mirq rst value 00h read value 00h bit 15 ? 0: when 1 will enable the corresponding interrupt and when 0 will mask that interrupt out. r/w. 4.4.2.6 fiq enable2 register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: fiqenable2 0x01ff802b (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: fiqenable2 0x01ff802a (not used) enable irq22 irqusb enable irq21 irqtimer2 enable irq20 irqsdaa enable irq19 irqdma5 enable irq18 irqssif enable irq17 irqsw enable irq16 irqsys rst value x0000000b read value 00h bit 3 ? 0: when 1 will enable the corresponding interrupt and when 0 will mask that interrupt out. r/w.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-52 conexant 100723a 4.4.2.7 external interrupt configuration register address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default eirqconfig 0x01ff802c irq16edge irq13edge irq11edge irq2edge irq16actlo irq13actlo irq11actlo irq2actlo rst value 00h read value 00h bit 7 ? 4: write a 1 will configure the corresponding external interrupt to be edge triggered and write a 0 will configure it to be level triggered. bit 3 ? 0: write a 1 will configure the corresponding external interrupt to be active low and write a 0 will configure it to be active high. 4.4.2.8 external interrupt clear register address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: eirqclear 0x01ff802d (not used) (not used) irq21clr irq10clr eirq16clr eirq13clr eirq11clr eirq2clr rst value xx000000b read value 00h bit 3 ? 0: firmware uses these bits to clear the corresponding edge triggered external interrupt which is latched in the interrupt controller. after writing a 1 to clear the interrupts, the bits reset themselves to 0. bit 5 ? 4: firmware uses these bits to clear the corresponding internal timer interrupts. after writing a 1 to clear the interrupts, the bits reset themselves to 0. 4.4.2.9 timer1 register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: timer1 0x01ff802f timer 1 value msb rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: timer1 0x01ff802e timer 1 value lsb rst value 00h read value 00h bit 15 ? 0: this is the timer value for the timer1 interrupt. this value will be loaded in a counter when the timer interrupt bit is enabled. the value loaded in this register is dependent on the siuclk frequency. this interrupt period can be programmed up to 50 ms with a programmable resolution. to write a new timer value into the register, the enable bit in the irq/fiq enable register must be disabled first; the new timer value is then written into the register and the enable bit is set to load the new timer value into the counter.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-53 4.4.2.10 timer2 register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: timer2 0x01ff8031 timer 2 value msb rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: timer1 0x01ff8030 timer 2 value lsb rst value 00h read value 00h bit 15 ? 0: this is the timer value for the timer2 interrupt. this value will be loaded in a counter when the timer interrupt bit is enable. the value loaded in this register is dependent on the siuclk frequency. this interrupt period can be programmed up to 50 ms with a programmable resolution (see table 4-10). to write new timer value into the register, the enable bit in the irq/fiq enable register has to be disabled first; the new timer value is then written into the register and the enable bit is then set to load the new timer value into the counter. the resolution of the timer1 and timer2 is dependent on siuclk and can be calculated as follows: tmrclk = (siuclk/b)/8 = iclk/8 (value of b is programmable) table 4-10. programmable resolution of timer1 and timer2 siuclk (mhz) b iclk (mhz) tmrclk (mhz) tmrclk (usec) 30 3 10 1.25 0.8 30 4 7.5 0.9375 1.067 37.5 4 9.375 1.171875 0.833 40 4 10 1.25 0.8
MFC2000 multifunctional peripheral controller 2000 hardware description 4-54 conexant 100723a 4.4.3 timing siuclk (internal) mirqn prtirqn(irq2) or gpio[8](irq11) or gpio[9](irq13) or irq16(sysirq) figure 4-14. external interrupt request timing note : the mfp2 000 chip resynchronizes mirqn, prtirqn, gpio[8], gpio[9], and irq16 signals internally. there are no setup time and hold time requirements for mirqn, prtirqn, gpio[8], gpio[9], mirqn, and irq16 signals with respect to sysclk. the four external interrupts prtirqn, gpio[8], gpio[9], and irq16 can also be programmed as edge triggered interrupts. in this case, the interrupt signals are implemented as clock into flip-flops with d-input either tied to high or low; again there is no setup and hold time requirements either. 4.5 dram controller (including battery dram) 4.5.1 functional description the dram controller interfaces to external memory devices and to the internal arm7 siu block. the dram memory space can be divided into two banks of memory which can be independently configured. the system clock rate that is supported can be up to 40mhz and can support the dram characteristics that are listed in the following tables addressing size: 512k, 1m, 4m, 16m organization: 4 bits, 8 bits, or 16 bits access speed: 50, 60, 70, 80 ns the maximum memory size that is supported for two memory banks is 32m. the dram chip sizes that are supported go up to 16m, but are limited to the row/column configurations that can be accommodated from the address multiplexing table (table 4-12) and the dram row/column configuration table 4-14). the number of dram access and refresh cycle wait states can be programmed from the dramctrl register. specifically, options to control the ras precharge width, ras low time, and cas low time are provided. the drive capability of the dram control signals can support a maximum of 50pf of loading capacitance. several types of external dram configurations can be supported: non-interleaved (8-bit or 16-bit data bus) and 2- way interleaved (16-bit data bus) (see table 4-11). memory bank 0 can be configured independently from memory bank 1.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-55 if a burst of data is sent to the dram, the dram controller will run in page mode once the initial access is completed. the maximum burst length is limited to 8 halfwords (i.e., the maximum burst length coincides with the cache line length) and is controlled by a burst signal that is generated from the siu. if a burst of data is being sent to the dram, but an octal address boundary occurs, the burst signal will turn off causing a rasn precharge. it is impossible to go across a page boundary without precharging the rasn signal. note: if a 16-bit wide memory structure is implemented, bursts of data must be 16-bit halfword bursts. 8-bit byte bursts are only allowed for an 8-bit wide memory structure. table 4-11. dram wait state configurations non-interleaved modes (8 or 16 bit interfaces) 1 cycle casn 30 mhz -50, -60 3 wait state, pg = 1 wait state 2 cycle casn 30 mhz -50, -60, -70, -80 3 wait state, pg = 2 wait state (read) 2 wait state, pg = 1 wait state (write) 37.5 mhz and 40 mhz -50, -60 5 wait state, pg = 2 wait state (read) 4 wait state, pg = 1 wait state (write) 37.5 mhz -70 5 wait state, pg = 2 wait state (read) 4 wait state, pg = 1 wait state (write) interleaved mode (16-bit interface) 30 mhz -50, -60, -70, -80 3 wait state, pg = 0,1,0 wait state (read)-even starting address, non octal boundary 4 wait state, pg=1,0,1 wait state (read)- odd starting address, non octal boundary 2 wait state, pg = 1 wait state (write) 37.5 mhz and 40 mhz -50, -60 5 wait state, pg = 0,1,0 wait state (read) 4 wait state, pg = 1 wait state (write) 37.5 mhz -70 5 wait state, pg = 0,1,0 wait state (read) 4 wait state, pg = 1 wait state (write) note : pg = page mode 4.5.1.1 memory bank structure dram address space can be selected in 2 separate memory blocks (bank 0: rasn[0] and cason[0] (8-bit) or cason[1:0] (16-bit) or cason[1:0] and casen[1:0] (interleaved), bank 1: rasn[1] and cason[0] (8-bit) or cason[1:0] (16-bit) or cason[1:0] and casen[1:0] (interleaved). separate control bits are provided in the backup configuration register to enable and disable (default) each of the memory banks. each bank has separate configuration controls and the address ranges of the two memory banks is continuous around the midpoint of the dram memory bank. the rasn[1] starting address is 03000000h and grows larger based on the size of the memory. the end of the rasn[0] bank ends at 03000000h and grows smaller from that point. the memory range is programmed through the address multiplexer selections for bank 0 and bank 1 in the dramctrl register.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-56 conexant 100723a 4.5.1.2 non-interleaved dram accesses non-interleaved dram accesses are available for 8-bit or 16-bit data bus. byte access is available for both 8-bit and 16-bit data bus and 16-bit halfword access is available for 16-bit data bus. dram early-write mode, normal read mode and page mode are supported. read-modify-write is not supported. note : 16-bit drams must have upper and lower cas?s in order to work with the dram controller. 8-bit bursts of data will not work with a 16-bit wide memory structure. 03000000h 02000000h 04000000h 03400000h bank 0 bank 1 note: in this example, bank 0 is 8m and bank 1 is 4m. 02800000h rasn[0] rasn[1] figure 4-15. dram bank/address map 4.5.1.3 2-way interleaved dram accesses the two-way interleaved dram interface can support up to four 16-bit wide devices a maximum of 8m deep. bank 0 is selected with rasn[0] and bank 1 is selected with rasn[1]. casen[1:0], cason[1:0], dwrn, doeon, doeen, addr, and data are common between the two banks. 2-way interleaving is limited to a 16-bit wide databus. 8-bit or 16-bit wide devices can be used. the arm cpu can write 32-bit words, 16-bit halfwords or bytes to the memory banks. the addressing to the interleaved drams starts with address bit 2. bits 1 and 0 are used internally to generate the proper cason[1:0] and casen[1:0] signals. when the memory structure is configured for two-way interleaving, byte bursts are not allowed. only bursts of 32-bit words or 16-bit halfwords are allowed. the maximum burst length is eight 16-bit halfwords. the burst length is controlled by the dramburst signal that is sent from the siu. the external memory structure can use the output enables directly to the memory device or for increased speed can use external bus transceivers. bus contention must be considered when the output enables are tied directly to a dram memory.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-57 table 4-12. address multiplexing ? ? ? ? part 1 address multiplexing register select option 000 select option 001 select option 010 select option 011 physical address row col. row col. row col. row col. a[13] a[22] a[13] a[23] a[13] a[24] a[13] a[25] a[13] a[12] a[21] a[12] a[22] a[12] a[23] a[12] a[24] a[12] a[11] a[20] a[11] a[21] a[11] a[22] a[11] a[23] a[11] a[10] a[19] a[10] a[20] a[10] a[21] a[10] a[22] a[10] a[9] a[18] a[9] a[19] a[9] a[20] a[9] a[21] a[9] a[8] a[17] a[8] a[18] a[8] a[19] a[8] a[20] a[8] a[7] a[16] a[7] a[17] a[7] a[18] a[7] a[19] a[7] a[6] a[15] a[6] a[16] a[6] a[17] a[6] a[18] a[6] a[5] a[14] a[5] a[15] a[5] a[16] a[5] a[17] a[5] a[4] a[13] a[4] a[14] a[4] a[15] a[4] a[16] a[4] a[3] a[12] a[3] a[13] a[3] a[14] a[3] a[15] a[3] a[2] a[11] a[2] a[12] a[2] a[13] a[2] a[14] a[2] a[1] a[10] a[1] a[11] a[1] a[12] a[1] a[13] a[1] a[0] a[9] a[0] a[10] a[0] a[11] a[0] a[12] a[0] table 4-13. address multiplexing ? ? ? ? part 2 address multiplexing register select option 100 select option 101 select option 110 select option 111 physical address row col. row col. row col. row col. a[11] a[24] a[13] a[23] a[13] a[24] a[12] a[22] a[12] a[10] a[23] a[12] a[22] a[12] a[23] a[11] a[21] a[11] a[9] a[22] a[11] a[21] a[11] a[22] a[10] a[20] a[10] a[8] a[21] a[10] a[20] a[10] a[21] a[9] a[19] a[9] a[7] a[20] a[9] a[19] a[9] a[20] a[8] a[18] a[8] a[6] a[19] a[8] a[18] a[8] a[19] a[7] a[17] a[7] a[5] a[18] a[7] a[17] a[7] a[18] a[6] a[16] a[6] a[4] a[17] a[6] a[16] a[6] a[17] a[5] a[15] a[5] a[3] a[16] a[5] a[15] a[5] a[16] a[4] a[14] a[4] a[2] a[15] a[4] a[14] a[4] a[15] a[3] a[13] a[3] a[1] a[14] a[3] a[13] a[3] a[14] a[2] a[12] a[2] a[0] a[13] a[2] a[12] a[2] a[13] a[1] a[11] a[1]
MFC2000 multifunctional peripheral controller 2000 hardware description 4-58 conexant 100723a table 4-14. dram row/column configuration memory size address multiplex setting supported/not supported row/column configuration 8-bit 16-bit 2-wy intrl. row column 256k x 8 000 000 000 supported 9 9 256k x 16 drams 000 000 000 supported 9 9 --- --- --- not supported 10 8 512k x 8 000 000 000 supported 10 9 1m x 8 001 001 001 supported 10 10 1m x 16 drams 001 001 001 supported 10 10 --- --- --- not supported 12 8 4m x 8 010 010 100 supported 11 11 4m x 16 drams 001 111 101 supported 12 10 --- --- --- not supported 13 9 16m x 8 011 110 --- supported 12 12 --- --- --- not supported 13 11 4.5.1.4 refresh operation dram refresh is performed automatically using the cas-before-ras method. three different refresh speeds are supported: slow, normal and fast. these speeds are selected by bits in the backup configuration register. the refresh time is based on the crystal oscillator frequency and the refresh rate that is selected. during prime power when it is time to refresh the dram, a cas-before-ras refresh cycle will be inserted. if the dram is being accessed when a dram refresh is requested, the refresh cycle is not inserted until the access is complete. the maximum burst length that the dram controller will see is 8 halfwords (i.e., the maximum burst length coincides with the cache line size). the maximum burst length is controlled by the siu with the dramburst signal that is sent to the dram controller.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-59 4.5.1.5 power down mode when the asic is powered down, the drams cannot be accessed. only dram refresh will continue on battery power (vdram). refresh timing is generated from a one shot and an internal gate delay circuit during battery powered operation. to ensure a smooth transition from vdd refresh to battery powered refresh, a control signal from the power reset block allows the dram controller to switch from vdd refresh to battery refresh when power is down. when the prime power is reapplied, the refresh logic switches back to vdd refresh. the refresh speed selected using the backupconfig register remains in force during the battery backed up mode. the dram backup time duration is defined by the two dram backup time bits in the backupconfig register. no backup, 1-2 days, 2-3 days, and infinite are the backup options. note: the amfpc asic uses a 3v process; therefore, if the dram memory structure is to be backed up, for the lowest power consumption 3 drams should be used. also, any external circuitry must also be battery powered. the output pads of the amfpc are only 5v tolerant during high z. the simplified block diagram for the dram controller is illustrated in figure 4-16. siu dram controller battery backed up logic dram state machine mux refresh speed rasn[1:0] cason[1:0] dwrn dram control register oneshot siuclk dramreq dramrdy dram cntl. dram addr external address databus oscclk, co_1day siu cntl switch battery backup register casen[1:0] doeon doeen dram state machine bank 0 bank 1 rtc battery dram battery figure 4-16. simplified dram controller block diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 4-60 conexant 100723a dram dram dram asic q- switch q- switch dwrn casen[0] casen[1] cason[0] cason[1] dwrn rasn[0] addr[11:0] rasn[0] addr[11:0] addr[u:0] data[7:0] rasn[1] cason[0] dwrn doeon (wron) data[15:0] data[15:0] bank 0 (interleaved) bank 1 (8-bit non-interleaved) wen oen oen wen doeon (wron) doeen (wren) oen wen figure 4-17. dram interface example figure 4-17 gives an example of how each bank of drams might be setup for non-battery back-up dram system. in this example, bank 0 is setup for an 8-bit non-interleaved memory bank and bank 1 is setup with a 16- bit 2-way interleaved dram bank. note : 1. dwrn is a battery backed-up signal and is ?high? during the battery back-up mode. all inputs of the prime powered logic will have ?no power? or ?low? during the battery back-up mode. therefore, all external logic, which uses dwrn, should be battery backed-up logic and should be gated with wrprotn to ensure that outputs are ?low? when the prime power is off for the battery back-up dram operation. 2. dwrn, caso[1:0]n and case[1:0]n are shared by both dram banks (ras[0]n and ras[1]n). if you only want to back up one bank by battery power, all shared signals should be separated by the external logic and should follow the rule in note 2.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-61 4.5.2 register description address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default dram control register (dramctrl1) $01ff8821 bank 1 address multiplexing bank 1 increase ras cycle time bank 1 2-cycle ras precharge bank 1 1-cycle rah bank 1 non-interleaved speed control 00 = fast mode 01 = normal mode 10 = slow mode 11 = n/a rst. value x0000000b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default dram control register (dramctrl1) $01ff8820 bank 0 address multiplexing bank 0 increase ras cycle time bank 0 2-cycle ras precharge bank 0 1-cycle rah bank 0 non-interleaved speed control 00 = fast mode 01 = normal mode 10 = slow mode 11 = n/a rst. value x0000000b read value 00h register description: the dram control register is used to program the two dram banks for the type of operation that is desired. bits 15-13: bank 1 address multiplexing this register controls the addressing multiplexing for bank 1 bit 12: bank 1 increase ras cycle time this register will add one cycle after the refresh cycle prior to ras precharge to meet t rc (rasn cycle time). this is needed in order to use 70 ns drams while running at 39mhz. bit 11: bank 1 2-cycle ras precharge this register will increase the rasn[1] precharge time from 1 to 2 clock cycles. bit 10: bank 1 1-cycle rah this register will increase the rasn[1] address hold time. when this bit is set, the address will be multiplexed 1 clock cycle after the falling edge of ras[1]n. the default setting will multiplex the row/column address ? clock cycle after the falling edge of ras[1]n. bit 9-8: bank 1 speed control these registers will control the speed of the dram interface for bank 1 when in the non-interleaved mode. this register controls the width of the casn signal. these bits are ignored in interleaved mode. bit 9 bit 8 non-interleaved operation: 0 0 casn is ? clock cycle wide. 0 1 casn is 1 clock cycle wide. 1 0 casn is 2 clock cycles wide for read and 1 clock cycle wide for write. 11 n/a bits 7-5: bank 0 addressing multiplexing: this register controls the addressing multiplexing for bank 0 (table 4-12).
MFC2000 multifunctional peripheral controller 2000 hardware description 4-62 conexant 100723a bit 4: bank 0 increase ras cycle time this register will add one cycle after the refresh cycle prior to ras precharge to meet t rc (rasn cycle time). this is needed in order to use 70 ns drams while running at 39mhz. bit 3: bank 0 2-cycle ras precharge this register will increase the rasn[0] precharge time from 1 to 2 clock cycles. bit 2: bank 0 1-cycle rah this register will increase the rasn[0] address hold time. when this bit is set, the address will be multiplexed 1 clock cycle after the falling edge of ras[0]n. the default setting will multiplex the row/column address ? clock cycle after the falling edge of ras[1]n. bits 1-0: bank 0 speed control these registers will control the speed of the dram interface for bank 0 when in the non-interleaved mode. this register controls the width of the casn signal. these bits are ignored in interleaved mode. bit 1 bit 0 non-interleaved operation 0 0 casn is ? clock cycle wide. 0 1 casn is 1 clock cycle wide. 10 casn is 2 clock cycles wide for read and 1 clock cycle wide for write. 11 n/a address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default backup configuration register (backupconfig) $01ff8099 (not used) (not used) internal power down select batrstn detected lockenn timeout detected sram enable 0 = disable 1 = enable bank 1 data interface size: 0 = 8-bit 1 = 16-bit bank 0 data interface size: 0 = 8-bit 1 = 16-bit rst. value xxxxx000b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default backup configuration register (backupconfig) $01ff8098 dram backup time 0 = no backup 1 = 1-2 days 2 = 2-3 days 3 = infinite days refresh rate 0 = normal 1 = slow oscillator speed 0 = 32.768 khz 1 = 65.536 khz bank 1 enable 0 = disable 1 = enable bank 0 enable 0 = disable 1 = enable bank 1 interleave enable 0 = non interleaved 1 = 2 way interleaved bank 0 interleave enable 0 = non interleaved 1 = 2 way interleaved rst. value 00h read value 00h register description: this register is set to all zeros when first powered up and is battery backed up with the rtc battery during power down. when a time out condition occurs, the rasn and casn signals are tri-stated. when prime power has returned from a power down sequence, the user will have to perform a checksum on the dram data to know if a time out has occurred since there is no indication that the dram battery has lost power. the user will have to wait 1ms before accessing the dram after prime power has returned. bits 15-14: not used bit 13: internal power down select 0 = pwrdwnn is generated by or-ing power_down1 with power_down2 1= pwrdwnn is generated by and-ing power_down1 with power_down2
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-63 note : power_down1 and power_down2 are output signals from the power-down detection circuit 1 and 2. bit12: betrstn detected this bit indicates that a betrstn occurred. to clear this bit, a 1 must be written to this bit. bit11: this bit indicates that a power down occurred, but no lockout was set within the 1-2 second period. the lockout timer initiated the lockenn to create the lockout condition. once the lockout condition occurs, if the power down signal is high, the chip will come out of reset after a pud1 delay. to clear this bit a 1 must be written to this bit. bit10: sram chip select enable this bit enables the sram chip select csn0. bit 9: bank 1 interface size this register defines whether the data bus to the bank 1 drams is 8 bits wide or 16 bits wide. an 8-bit wide dram interface uses rasn[1] and cason[0]. a 16-bit wide non-interleaved dram interface uses rasn[1] and cason[1:0]. a 16-bit wide interleaved dram interface uses rasn[1], casen[1:0], and cason[1:0]. bit 8: bank 0 interface size this register defines whether the data bus to the bank 0 drams is 8 bits wide or 16 bits wide. an 8-bit wide dram interface uses rasn[0] and cason[0]. a 16-bit wide non-interleaved dram interface uses rasn[0] and cason[1:0]. a 16-bit wide interleaved dram interface uses rasn[0], casen[1:0], and cason[1:0]. bits 7-6: dram battery backup time these bits control the amount of time that the dram controller will spend refreshing the drams when in the battery backup mode. after reset when the cpu is being released to run, the cpu will not be able to write data to bits 7 and 6 of the backupconfig register immediately since the immediate write will not take effect. the cpu must wait at least one oscillator clock cycle before writing data into bits 7 and 6. bit 7 bit 6 battery backup duration: 0 0 no battery backup (default) 0 1 1-2 days 1 0 2-3 days 1 1 infinite bit 5-4: dram refresh rate these bits are used to set up the dram refresh rate. see the following table:
MFC2000 multifunctional peripheral controller 2000 hardware description 4-64 conexant 100723a refresh speed: (bit 5) oscillator speed: (bit 4) refresh speed: description: 0 0 normal rtc crystal frequency = 32.768 khz, refresh clock = the crystal frequency = 32.768 khz, the refresh cycle time = 15.625 ms/1024 cycles. 0 1 fast rtc crystal frequency = 65.536 khz, refresh clock = the crystal frequency = 65.536 khz, refresh cycle time = 7.8125 ms/1024 cycles. 1 0 slow rtc crystal frequency = 32.768 khz, refresh clock = the crystal frequency/8 = 4.096 khz refresh cycle time = 125 ms/1024 cycles. 1 1 slow rtc crystal frequency = 65.536 khz, refresh clock = the crystal frequency/16 = 4.096 khz refresh cycle time = 125 ms/1024 cycles. bits 3: bank 1 enable this bit controls whether or not the bank 1 drams will be enabled. the enable signal will allow cas before ras refresh to occur based on the non-interleave or interleave setting. if the bank setting indicates a non-interleaved mode, rasn[1] and cason[0] (8-bit mode) or cason[1:0] (16-bit mode) will refresh the dram. if the bank setting indicates an interleaved mode, rasn[1], cason[1:0] and casen[1:0] will refresh the dram. dwrn will be high during refresh. if bank 1 is disabled, ras[1]n will be tri-stated and all appropriate casn?s will be tri-stated based on mode settings. bit 2: bank 0 enable this bit controls whether or not the bank 0 drams will be enabled. the enable signal will allow cas before ras refresh to occur based on the non-interleave or interleave setting. if the bank setting indicates a non-interleaved mode, rasn[0] and cason[0] (8-bit mode) or cason[1:0] (16-bit mode) will refresh the dram. if the bank setting indicates an interleaved mode, rasn[0], cason[1:0] and casen[1:0] will refresh the dram. dwrn will be high during refresh. if bank 0 is disabled, ras[0]n will be tri-stated and all appropriate casn?s will be tri-stated based on mode settings. bit 1: bank 1 interleave enable this register defines whether the bank 1 drams are to be accessed using 2-way interleave or non interleaved access. 2-way interleaved access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface size bit for bank 1 is ignored by the dram controller, but is used by the siu to output the data correctly). bit 0: bank 0 interleave enable this register defines whether the bank 0 drams are to be accessed using 2-way interleave or non interleaved access. 2-way interleaved access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface size bit for bank 1 is ignored by the dram controller, but is used by the siu to output the data correctly).
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-65 4.5.3 brief timing no matter which mode you use and which address you access, the dram access timing is lined up with the octal halfword boundary. siuclk rasn[0] casen[0] arm addr or dma addr siuaddr extaddr row col col col col row col octal boundary col a a+2 a+4 note: in this example, a =...01010, a+2=...01110, a+4=...10000 a a+1 a+2 a+3 a+4 a+5 dwrn doeen data figure 4-18. 8-bit memory data bus the timing diagram illustrates an 8-bit memory data bus, a burst of halfword transfers (3 halfwords) from the arm7 or dma, for ? cycle casn and pg = zero wait states (non-interleaved). it also illustrates the octal halfword boundary that will cause the siu to terminate the burst and cause the dram controller to regenerate the rasn precharge time. this interface speed can only be used at slow frequencies. siuclk rasn[1] cason[1:0] armaddr siuaddr extaddr row col col col col a a+4 a a+2 a+4 a+6 dwrn data doeon figure 4-19. 16-bit memory data bus
MFC2000 multifunctional peripheral controller 2000 hardware description 4-66 conexant 100723a the timing diagram illustrates a 16-bit memory data bus, a burst of word transfers (2 words) from the arm7 for full clock width casn and pg = one wait state (non-interleaved). it also illustrates that the octal halfword boundary doesn?t occur in the middle of the burst of word transfers. siuclk rasn[0] casen[0] dwrn arm addr or dma addr siu addr ext addr a row col data a doeen data figure 4-20. casn non-interleaved 8-bit dram read the timing diagram illustrates a two clock cycle casn non-interleaved 8-bit dram read (non burst mode). this configuration illustrates the row/column address multiplex occurring 1 cycle after rasn. siuclk rasn[0] casen[1:0] dwrn arm addr or dma addr siu addr ext addr a +4 a row +2 col +6 +4 col data doeon doeen cason[1:0] siu p_addr a +2 +6 +4 col +8 +10 +8 +8 +10 +2 +6 +10 note: in this example, a[2:0] = 00x. also, the external address is created from the pipelined siu address; however, address pins a1 and a0 are not connected to the external memories. figure 4-21. 2-way interleaved memory with halfword bursts of data
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-67 this example illustrates a read of two-way interleaved memory with halfword bursts of data (6 halfwords). it also illustrates that the octal halfword boundary doesn?t occur in the middle of the burst of halfword transfers. it assumes external drivers to minimize the data bus contention and to insure that the data has enough setup time to clk. this waveform also illustrates, increased rasn precharge time and increased address multiplexing time. byte bursts of data are not allowed when a 16-bit memory structure is used. siuclk rasn[0] casen[1:0] dwrn arm addr siu addr ext addr a a+4 a row +2 col +6 +4 col data doeon doeen cason[1:0] siu p_addr a +2 +6 +4 col +8 +10 a+8 +8 +10 figure 4-22. 2-way interleaved dram read (3 words) the timing diagram illustrates a two-way interleaved dram read (3 words). it assumes external drivers to minimize the data bus contention and to insure that the data has enough setup time to clk. this waveform also illustrates, increased rasn precharge time and increased address multiplexing time. siuclk rasn[1] casen[1:0] dwrn arm addr siu addr ext addr a a+4 a+8 a row col a+4 a+8 col a+2 a+6 a+10 data doeon doeen cason[1:0] col figure 4-23. 2-way interleaved dram write
MFC2000 multifunctional peripheral controller 2000 hardware description 4-68 conexant 100723a the timing diagram illustrates two-way interleaved dram write. this configuration assumes that the data bus is available to the dram with enough setup time to the casn falling edge. in addition, this configuration has a 2- cycle wide rasn and allows one cycle after the falling edge of rasn before the row/column address mux. siuclk rasn[1] casen[1:0] dwrn cason[1:0] trp tras a refresh cycle tcp figure 4-24. refresh cycle the timing diagram illustrates a refresh cycle. t ras is three cycles wide to accommodate frequency ranges up to 40 mhz. this timing is used during prime power refresh. during battery backup, a custom refresh circuit is used to generate refreshed timing based on the oscillator clock. 4.5.4 detailed timing measurements t rd t cd access with 1 or 2 wait states access with 0 wait states siuclk rasn[1:0] casen[1:0], cason[1:0] dwrn (write) t rd t cd0 t cd t dw t dw col col col a[x:0] (option 1) row col col col a[x:0] (option 2) t rah1 t rah2 t csu t csu0 dwrn (read) t cdo note:1 note:2 row figure 4-25. dram timing ? ? ? ? read, write and wait states for non-interleave mode
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-69 t rd t cd siuclk rasn[1:0] casen[1:0] cason[1:0] doen[1:0] (wren/wron) t rd t cd t cd t cd dwrn t dw t dw note:1 figure 4-26. dram timing for 2-way interleave write t rd t cd siuclk rasn[1:0] casen[1:0] cason[1:0] doen[1] (wron) t rd t cd t cd t cd t cd t cd doen[0] (wren) t oed t oed t oed t oed t oed t oed note:1 figure 4-27. dram timing ? ? ? ? read for 2-way interleave mode
MFC2000 multifunctional peripheral controller 2000 hardware description 4-70 conexant 100723a t crd t rcas siuclk rasn[1:0] casen[1:0], cason[1:0] dwrn t rras figure 4-28. dram refresh timing xin rasn[1:0] casen[1:0], cason[1:0] dwrn t rras t r cas t crd t crd figure 4-29. dram battery refresh timing
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-71 table 4-15. dram timing parameters parameter symbol min. max. units rasn delay t rd 20 ns casn delay (0 wait state) t cd0 20 ns casn delay t cd 20 ns casn address setup (0 wait state) (10mhz) t csu0 7 ns casn address setup (30 mhz) t csu 7 ns rasn address hold 1 t rah1 3 ns rasn address hold 2 t rah2 3 ns dwrn delay t dw 20 ns oe delay t oed 20 ns casn pulse width t rcas 30 500 ns rasn pulse width t rras 30 500 ns casn to rasn delay t crd 5 200 ns notes : 1. bit 2 of the dram control register sets this time to ? or 1 clock cycle. 2. bit 8 and 9 of the dram control register sets this time to 1 or 2 clock cycles. 4.5.5 software operation special cautions ? the backup configuration register is set to 0000h the initial power up only. this register is backed up during battery power mode. ? dram control signals are tri-stated during battery power if the backup timer is set to 0 or the backup time expires, regardless of how the enable bits are set. ? after a reset occurs and the cpu is released to run, the cpu cannot write to the backup configuration register until one oscclk cycle has passed. ? during power-up, the firmware must pay attention to the power up dram requirements specified in the dram data books. typically, drams cannot be accessed for 200 s and then must have 8 casn before rasn refreshes occur before accessing the drams. ? within the dram memory address space memory bank mirroring is allowed. firmware will have to determine the memory size.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-72 conexant 100723a 4.6 flash memory controller the flash memory controller provides an interface for both nand and nor type flash memory devices. up to two nor type flash memory devices or two nand type devices can be connected to the asic. fcs0n and fcs1n pins are the flash memory control pins. fwrn and frdn are the flash read and write signals for nand type devices. additional pins are required to interface to nand type flash memory devices. gpio pins can be used as nand type flash memory control signals. figure 4-30 shows the structure of the flash controller. it consists of an address and chip select generator block and a read/write control block. the address and chip select generator block provides up to 21 address lines and 2 chip select signals for the flash memory devices. the read/write control block provides read and write strobes for nand type devices. 4.6.1 supported flash memory the flash memory controller supports the following types of flash memory and their equivalents: flash memory size type intel 28f400bl/28f004bl-150 512 kb nor type 28f400bx/28f004bx-80, -120 512 kb nor type amd am29f040-70, -90, -120, -150 512 kb nor type samsung km29n040/080-150 512 kb/1 mb nand type note: this asic also supports 1mb and 2mb nor-type flash memory if the specified timing can be matched. 4.6.2 functional description 4.6.2.1 interfacing flash memory the two types of flash memory that are supported require separate interface control options. nor type devices are bus oriented and can be connected to the cpu bus. the asic provides address signals to access the memory space and provides the chip select signals. nand type devices are special purpose peripherals with a specialized interface requiring no address bus signals. the asic will use dedicated pins and gpio pins to interface with the nand flash control and status lines. 4.6.2.2 nor type flash memory nor type devices can be used for both firmware code memory and for data memory. accesses are performed using normal bus operations. reading data is performed with a bus read. programming bytes or erasing sectors requires multiple bus cycles. the cpu writes the command sequences required by the flash memory; then it polls the flash memory?s status until the operation is complete. the data address space is available in two separate blocks; the first block of memory is from 00800000h to 009fffffh (2mbyte block) and the other is from 00a00000h to 00bfffffh (2mbyte block). when the cpu accesses the address range 00800000h - 009fffffh, fcs0n is activated. when the cpu accesses the address range 00a00000h - 00bfffffh, fcs1n is activated. when using fcs0n and fcs1n for nor-type flash memory, the nand-type bit (bit 6) of the flashctrl register must be set to 0. the flashctrl register is described in the siu section of the hardware description. the nor type flash interface consists of: ? fcsn[1:0]: the two flash device selection signals. to use fcsn[1:0], bit 6 of the flashctrl register must be set to 0. ? a[20:0]: the external address bus for 2mb address range. ? rdn and wren/wron: the external bus read and write strobes. ? d[15:0]: the external data bus.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-73 4.6.2.3 nand-type flash memory nand type devices can only be used for data memory. nand type flash devices have no address bus. command, address and data are passed through the external data bus. accesses are accomplished by first setting the appropriate flash cs and control signals through the fcsn[1:0] and gpio pins. the actual bus transfer is performed by accessing the nandflsh register. when accessing the nandflsh register, the appropriate flash data strobe is activated, frdn for read operations and fwrn for write. frdn and fwrn are also controlled by the wait state setting in the flashctrl register. the nand-type bit in the flashctrl register must be 1. ? fcsn[1:0]: the device selection signals for the nand type flash devices. fcs0n and fcs1n pins act as gpo pins. fcsn[1:0] pins output values which are set to bit 8 and bit 9 of the flashctrl register. note: if fcs0n/pwm[1] and fcs1n/pwm[2] pins are programmed as pwm, any two available gpo?s or gpio?s can be used to generate fcs[1:0]n for nand-type flash memory. ? fcle: the flash command latch enable. it is programmable via a gpio pin. fcle activates the commands sent to the command register. ? fale: the flash address latch enable. it is programmable via a gpio pin. fale activates the controls for address or data to the internal address or data registers of the flash device. ? frdy: the flash ready signal. it can be read from a gpio pin. frdy indicates the status of the flash device operation. ? frdn: the flash read enable signal. it is a hardware generated signal. it is multiplexed on gpio[1] and configured in the gpioconfig register. frdn enables the data from the flash memory device onto its i/o bus. this signal is active when the cpu reads the nand flash location of 01ff8824h. ? fwrn: the flash write enable signal. it is a hardware generated signal. it is multiplexed on gpio[0] and configured in the gpioconfig register. fwrn controls writes to the i/o bus. this signal is active when the cpu writes to the nand flash location of 01ff8824h. ? wrprotn: the write protect signal is driven low to protect the flash devices from inadvertent writes during power transitions. it is also controlled by writing to the ?prime power write protect? bit (bit 11) of the flashctrl register. ? d[15:0]: the external data bus. flash address & chip select generator (in siu block) flash read/write control addr[25:0] fadd[20:0] fcsn[1:0] frdn fwrn siuclk rwn figure 4-30. flash control block diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 4-74 conexant 100723a 4.6.3 timing all accesses can be performed from zero to seven wait states. the number of wait states is programmable in the flashctrl register. during write operations, if one to seven wait states is used, the earlyoff option must be set in the flashctrl register. the earlyoff option is ignored with zero wait state. wait states are generated to accommodate slow memory devices, for more details of how the control signals are changed with an inserted wait state, refer to the timing diagram figure 4-31. ? nand-type flash for this type of flash, addresses and data are passed through the external data bus. during read operations, the device selection is one of the two flash chip select signals fcsn[1:0], frdn is the flash read enable signal from the bus interface. fcle and fale must be low (inactive) during reads. for zero wait state access, fwrn and frdn are only half siuclk cycle (like rdn and wrn of the normal bus operation). during program/erase operations, the device selection is one of the fcsn[1:0] signals. command, address and data are all written through the external data bus. the flash command latch enable (fcle ) and the flash address latch enable (fale) signals are the controls for writing to the command or the address register respectively. fcle and fale must be low (inactive) during a data write to the flash devices. ? nor-type flash accesses are performed using normal bus operations. during program/erase operations, the device selections are the two flash chip select signals fcsn[1:0], addresses are latched on the falling edge of the flash write enable signal wren/wron, and data is latched on the rising edge of wren/wron.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-75 t fcsd t fd sysclk fcsn[1:0] gpio[0] (fwrn) t fcsd t fd in d[15:0] (read) out d[15:0] (write) t fdsu t wdd gpio[1] (frdn) t fd t fd t wdh t ald t ald fale (gpio) fcle (gpio) t cld t cld figure 4-31. nand-type flash memory access with two wait states parameter symbol min. max. units fcsn delay t fcsd 16 ns flash read/write delay t fd 16 ns flash read data setup t fdsu 8 ns flash write data delay t wdd 21 ns flash write data hold t wdh 0 ns flash address latch delay t ald 16 ns flash command latch delay t cld 16 ns
MFC2000 multifunctional peripheral controller 2000 hardware description 4-76 conexant 100723a 4.6.4 register description address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: nandflash (nandflsh) 00c00001h (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: nandflash (nandflsh) 00c00000h reading this location activates the frdn signal. writing to this location activates the fwrn signal. no physical register exists for this location. rst. value xxh read value 00h register description: this register is the io address space for the nand type flash. reading this register activates the frdn signal. writing to this register activates the fwrn signal. fcle, fale, and frdy must be setup through the gpio pins and fcsn[1:0] must be setup through the flashctrl register prior to accessing the nandflash register. fcle, fale, and frdy must be cleared through the gpio pins and fcsn[1:0] must be cleared through the flashctrl register after the register access. data written to this register is output on the data bus. when reading this register the flash memory data is placed on the internal cpu bus. the nandflash register is only an address location; no register actually exists. 4.7 dma controller 4.7.1 general description ? the amfpc is equipped with thirteen physically arbitrated dma channels assigned to either internal or external requests. ? each channel provides its own 26-bit address for data access ? the dma channel address registers are made up of two programmable half word read/write registers, making up a 26-bit counter (64mb). ? minimum dma acknowledge delay is 2 system clocks. ? maximum dma acknowledge delay depends on the number of pending higher priority dma requests and the length of associated bus cycles including wait states and halt states due to dma/dram refresh cycle collisions. ? channel specific unique features ? double buffered address and block size this channel is equipped with a double buffered dma address counter and block size register. this allows firmware to set up the dma address and block size values for the next block access while the current one is active. when the dma channel reaches it?s block size limit it issues an interrupt, and if a new value has been written into the buffers (buffer loaded flag is set), this value is transferred to the address counter and/or block size register. the interrupt is cleared upon writing to the block size buffer register. ? dma block size an access block size counter is available to limit the number of dma access in a given block. once this counter is set, it will keep track of the number of dma access. once the limit has been reached a cpu interrupt will be set and no further accesses will be allowed until the register is reset. the irqdma is activated at the falling edge of dmaack.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-77 ? addressing modes all of the dma channels increment by 2 after each access. the external channels 1 and 2, can be set to increment by 1 for byte wide peripherals. the count enable register allows the user to select which address will increment after each access. however, channels 2 and 3 have the additional functionality allowing them to increment or decrement by a specified amount. channel 2 is controlled by the values in it?s control register. channel 3 is controlled by control signals generated in the bit rotation logic. ? priority shows the overall channel priority in the dma request arbitrator, with 1 as the highest. ? uninterrupted burst mode allows the requesting device to hold the burst dma request active (pseq), to transfer multiple bytes of uninterrupted data. if higher priority requests occur during the burst operation they will be ignored. this operation is mainly for high speed dram access. also during this mode, the read/write control and the count controls must remain static. ? throttle control a throttle value can be set to allow 1 dma access per a given time period. the throttle time period is a product of the value set and the system clock. ? logical channels this single physical dma channel is equipped with multiple logical channels that operate independent of each other. only one logical can be active at any time. 4.7.1 dma mode summary table 4-16. feature matrix features channel double buffered control block size limit address increment address decrement address jump priority u-i burst mode other features 0 ? 1 logical 1 2 2 ? ? 3 byte 3 ?? 4 4 ? 7 5 ? 8 6 ? 9 throttle 7 ? 10 8 ? 11 9 ? 12 10 ? 13 throttle 11 ? 5 12 ? 6 throttle
MFC2000 multifunctional peripheral controller 2000 hardware description 4-78 conexant 100723a each of the dma channels, its function, and its characteristics are provided in table 4-17. table 4-17. dma channel functions and characteristics dma channel function characteristics 0 1 usb data to/from memory for pc print, pc fax tx, pc fax rx, pc scan dma block size limit with cpu interrupt via pio/usb interrupt, 4 logical dma channels, dma address and block size double buffered, each read/write selectable, halfword dma data access only. 1 external dma access only. normal and delayed ack, read/write selectable, byte and halfword dma data access selectable. 2 external dma request only bit rotation access (output) address jump control, dma block size limit with interrupt to irq controller, burst mode, double buffered control registers read/write, external request (generates a disdrive to disable the bus if output drivers to for external memory writes.) external request to the dma controller may be delayed from 1 to 2 clocks for synchronization. 3 bit rotation access (input) address jump control (controlled by bit rotation block see table4.8.2-1) read only, internal request. (mas is always set to ? word) 4 countach to arm memory (c2a) data write only, halfword dma data access only 5 arm memory to countach (a2c) data read only, dma block size limit (16 kb), interrupt to irq controller halfword dma data access only. 6 read/write t4 uncoded data from/to line buffer to/from t4 logic throttle control read/write, internal request (mas is always set to ? word) 7 read t.4 reference line from the line buffer to t.4 logic read only, internal request (mas is always set to ? word) 8 t4 resolution converted data, line buffer access disable address count for read modify write read/write, internal request, read modify write control (mas is always set to ? word) 9 bi-level resolution conversion logic dma block size limit. interrupt to irq controller (mas is always set to ? word) 10 read/write t4 coded data from/to page memory to/from t4 logic throttle control address block size limit, interrupt to irq controller read/write, internal request (mas is always set to ? word) 11 p1284 to memory dma block size limit with cpu interrupt via pio interrupt, read/write (control bit), internal request 12 memory to p1284 dma block size limit with cpu interrupt via pio interrupt, read/write (control bit), internal request (mas is always set to ? word) notes: 1. dma channel 0 has the highest priority. 2. "ad" means address.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-79 4.7.2 dma operation and timing the dma controller arbitrates dma requests from all sources (internal and external), and then acknowledges the request of the source with the highest priority at the start of the next bus cycle. after each request has been issued, the associated acknowledge signal is activated with a minimum delay of 2 internal clock cycles. the maximum delay is dependent on both the number of pending higher priority dma requests, and the length of the associated bus cycles (including wait states and halt states due to dma to dram and refresh cycle collisions). the dma controller informs the bus control logic (siu), and provides the address and read/write signal prior to the next bus cycle. at the time of the next bus cycle, the siu routes the address and data onto the proper bus. if the external bus is required to complete the dma transfer, the dma controller notifies the external bus control logic, which in turn halts the cpu. after the completion of a dma cycle, the dma controller increments or decrements the dma address counter. a non-maskable interrupt (sysirq) to the cpu allows the active dma to be completed, but locks-out all other dma acknowledge signals in the event of a power down condition. dma channel 3 address progression is controlled by the bit rotation logic and is not effected by the dma acknowledges like other channels. the bit rotation logic provides an address progression value, an increment/ decrement (add/subtract) control and a count strobe. when the strobe is held active during the rising edge of the siuclk, the progression value is either added or subtracted from the current address value. below is a table showing the control bit assignments. table 4-18 dma channel 3 control bit assignment count control assignments countcntl(11) count strobe na countcntl(10) dec_incn na countcntl(9) cnt_by_32k add_value(15) countcntl(8) cnt_by_16k add_value(14) countcntl(7) cnt_by_8192 add_value(13) countcntl(6) cnt_by_4096 add_value(12) countcntl(5) cnt_by_2048 add_value(11) countcntl(4) cnt_by_1024 add_value(10) countcntl(3) cnt_by_512 add_value(9) countcntl(2) cnt_by_4 add_value(2) countcntl(1) cnt_by_2 add_value(1) countcntl(0) cnt_by_1 add_value(0) 4.7.3 timing 4.7.3.1 internal dma requests dma requests are sourced by sub-blocks or peripherals within the asic or by an external device (ch 0 or 1). some logic blocks may source multiple dma request lines. for example, the t4 logic requires 3 request lines: input data, reference data and output data. these sources will issue dma request signals, and the sequential access indicator, synchronized to the rising edge of siuclk . during the bus cycle that the requests are received, the controller will inform the siu that the next bus cycle will be a dma cycle. the dma controller also provides the address, the sequencial access , and read/write control information to the siu. the siu will then activate the dma bus acknowledge signal when the dma controller becomes the bus master. on the first rising edge of the siuclk after the dma bus acknowledge signal becomes active, the peripheral dma acknowledge to the requesting peripheral will be set high indicating the start of the dma cycle. for a dma single cycle write, the requesting device must drive data onto the bus during activation of the peripheral dma acknowledge signal. and for a single
MFC2000 multifunctional peripheral controller 2000 hardware description 4-80 conexant 100723a cycle dma read the requesting device must capture the data on the falling edge of the peripheral dma acknowledge. if a sequential dma access burst is desired, the peripheral must also activate the sequential access indicator at the time of the initial request and must be cleared at the end of the next to the last dma cycle. the dma request must be deactivated during the final dma cycle, on the 1 st rising edge of the siuclk. the peripheral must also capture (read), or drive the next datum onto the data bus on each rising edge of the siuclk when the dma acknowledge is active. during sequential burst accesses the read/write control and dma address count controls must remain static. 4.7.3.2 external dma requests the external device activates the dma request signal (dmareq) at any time when it wants to do the single dma access operation. the MFC2000 chip double synchronizes the dmareq signal internally to avoid the meta- stable case. after external dma request has been issued, the associated acknowledge signal is activated with a minimum delay of 5 internal siuclk cycles. the external device must deactivate dmareq after the associated acknowledge signal is activated and before the end of this dma cycle. if the dma request continues to be activated by the external dma requesting device, the external dma requesting device will get the second dmaack signal for the next single data transfer, when system bus is ready. the MFC2000 chip continues to perform single dma access as long as the dmareq is kept active by the external dma requesting device. dmaack is used similarly as chip select to indicate the dma access cycle is ready for the external dma requesting device. the delay path within the MFC2000 is longer for dmaack than for rdn; however, the actual amount of skew between the two signals is dependent on their relative loading at the system board level. if rdn has excessive delay, the dmaack can be programmed to extend it an extra half siuclk cycle. siuclk ext. dmaack dma address ext. address bus dma data ext. data bus ext. dmareq tdrs tad tdadn tdih trd tdadf rdn dma cycle trd figure 4-32: external dma read timing (single access, one wait state)
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-81 siuclk ext. dmaack dma address ext. address bus dma data ext. data bus ext. dmareq tdrs tad tdadn tdoh twd tdadf wren dma cycle twd figure 4-33. external dma write timing (single access, one wait state) parameter symbol min max units rdn delay (ext. load = 50pf) trd ? 25 ns wrn delay (ext. load = 50pf) twd ? 25 ns address delay (ext. load = 50pf) tad ? 24 ns dmaack on delay time (ext. load = 15pf) tdadn ? 10 ns dmaack off delay time (ext. load = 15pf) tdadf ? 5ns dma input data hold tdih 8 ? ns dma output data hold (ext. load = 50pf) tdoh 8 25 ns rasn delay (ext. load = 40pf) trasd ? 25 ns casn delay (ext. load = 40pf) tcasd ? 20 ns dwrn delay (ext. load = 40pf) tdwd ? -20 ns notes : 1. siuclk is the internal system interface clock. these values is for siuclk = 30 mhz. 2. the external dma request set-up time (tdrs) is not required because this input is double synchronized internally for the meta-stable case.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-82 conexant 100723a 4.7.4 usb block diagrams below is a block diagram depicting the four usb logical channels. each logical channel shows the double buffering of the address and block registers. the right side of the diagram shows the common counters for the block and address. also shown is the feedback path from the counters to the registers used upon usb acks. the select signal for the logical channels are shown at the bottom of the diagram. address 1 address 2 block 1 block 2 lch1 address 1 address 2 block 1 block 2 lch2 address 1 address 2 block 1 block 2 lch3 address 1 address 2 block 1 block 2 lch4 addr counter block counter ipb data channel select note: selecting channel will load current registers to counter address feedback block feedback adr_out blk_out to ipb data out figure 4-34. usb logical channels block diagram 4.7.4.1 usb logical channel assignments ? ch1: scan mem to pc, dma read only ? ch2: print pc to mem, dma write only ? ch3: fax rx mem to pc, dma read only ? ch4: fax tx pc to mem, dma write only
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-83 4.7.5 dma controller registers usb logical channel assignments dma channels 1 ? 12 addressing is controlled by the following registers. note : if the dma address counter points to an invalid location, invalid data is read or written address: chcsl[10:0] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma low counter (dmaicntlo) dma0-12 addr. bit 15 dma0-12 addr. bit 14 dma0-12 addr. bit 13 dma0-12 addr. bit 12 dma0-12 addr. bit 11 dma0-12 addr. bit 10 dma0-12 addr. bit 9 dma0-12 addr. bit 8 rst. value 00h read value 00h address: chcsl[10:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma low counter (dmaicntlo) dma0-12 addr. bit 7 dma0-12 addr. bit 6 dma0-12 addr. bit 5 dma0-12 addr. bit 4 dma0-12 addr. bit 3 dma0-12 addr. bit 2 dma0-12 addr. bit 1 dma0-12 addr. bit 0 rst. value 00h read value 00h dma channel 0 ? 12 lower address counter value dmausb0cntlo 01ff81c8-c9 dmausb1cntlo 01ff81ce-cf dmausb2cntlo 01ff81d4-d5 dmausb3cntlo 01ff81da-db dma1cntlo 01ff8184-85 dma2cntlo 01ff8188-89 dma3cntlo 01ff8190-91 dma4cntlo 01ff8194-95 dma5cntlo 01ff8198-99 dma6cntlo 01ff819c-9d dma7cntlo 01ff81a0-a1 dma8cntlo 01ff81a4-a5 dma9cntlo 01ff81a8-a9 dma10cntlo 01ff81ac-ad dma11cntlo 01ff81e0-e1 dma12cntlo 01ff81e6-e7
MFC2000 multifunctional peripheral controller 2000 hardware description 4-84 conexant 100723a address: chcsh[10:0] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma hi counter (dmaicnthi) not used not used not used not used not used not used dma0-12 addr. bit 25 dma0-12 addr. bit 24 rst. value 00h read value 00h address:chcsh[10: 0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma hi counter (dmaicnthi) dma0-12 addr. bit 23 dma0-12 addr. bit 22 dma0-12 addr. bit 21 dma0-12 addr. bit 20 dma0-12 addr. bit 19 dma0-12 addr. bit 18 dma0-12 addr. bit 17 dma0-12 addr. bit 16 rst. value 00h read value 00h dma channel 0 ? 12 upper address counter value dmausb0cnthi 01ff81ca-cb dmausb1cnthi 01ff81d0-d1 dmausb2cnthi 01ff81d6-d7 dmausb3cnthi 01ff81dc-dd dma1cnthi 01ff8186-87 dma2cnthi 01ff818a-8b dma3cnthi 01ff8192-93 dma4cnthi 01ff8196-97 dma5cnthi 01ff819a-9b dma6cnthi 01ff819e-9f dma7cnthi 01ff81a2-a3 dma8cnthi 01ff81a6-a7 dma9cnthi 01ff81aa-ab dma10cnthi 01ff81ae-af dma11cnthi 01ff81e2-e3 dma12cnthi 01ff81e8-e9
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-85 address:ch0cscntl bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma 0 configuration (dma0config) $xx81b1 channel enable lc3 channel enable lc2 channel enable lc1 channel enable lc0 read/write mode lc3 read/write mode lc2 read/write mode lc1 read/write mode lc0 rst. value 00h read value 00h address:ch0cscntl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma 0 configuration (dma0config) $xx81b0 not used not used irq lc3 irq lc3 irq lc3 irq lc3 not used dma0 enable rst. value 00h read value 00h bit 15-12: logical channel enable setting the bit to 1 will allow operation of the logical channel, setting the bit to 0 will disable the channel and clear it?s registers. bit 11-8: read/write mode select. selects the data direction. read = 1, write = 0 bit 5-2: interrupts from the individual logical channels. clear by writing to the block size register. bit 0: setting this bit to 1 will enable dma channel 0. setting this bit to 0 will fore all of the logical channels into their reset state. address: chcsl[10:0] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dmausb low counter (dmaicntlo) dma0-10 addr. bit 15 dma0-10 addr. bit 14 dma0-10 addr. bit 13 dma0-10 addr. bit 12 dma0-10 addr. bit 11 dma0-10 addr. bit 10 dma0-10 addr. bit 9 dma0-10 addr. bit 8 rst. value 00h read value 00h address: chcsl[10:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dmausb low counter (dmaicntlo) dma0-10 addr. bit 7 dma0-10 addr. bit 6 dma0-10 addr. bit 5 dma0-10 addr. bit 4 dma0-10 addr. bit 3 dma0-10 addr. bit 2 dma0-10 addr. bit 1 dma0-10 addr. bit 0 rst. value 00h read value 00h ? dmausb channel 0-3 lower address counter value. address will only count by 2. ? reading this register will return the active address value when the last usback occurred. note : this register is double buffered. writing to this location twice will load the active register as well as the buffer register. upon a block limit interrupt, the buffer value will be activated therefor a new buffered value should be written to this register. dmausb0cntlo 01ff81c8-c9 dmausb1cntlo 01ff81ce-cf dmausb2cntlo 01ff81d4-d5 dmausb3cntlo 01ff81da-db
MFC2000 multifunctional peripheral controller 2000 hardware description 4-86 conexant 100723a address: chcsh[10:0] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dmausb hi counter (dmaicnthi) not used not used not used not used not used not used not used not used rst. value 00h read value 00h address:chcsh[10: 0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dmausb hi counter (dmaicnthi) dma0-10 addr. bit 23 dma0-10 addr. bit 22 dma0-10 addr. bit 21 dma0-10 addr. bit 20 dma0-10 addr. bit 19 dma0-10 addr. bit 18 dma0-10 addr. bit 17 dma0-10 addr. bit 16 rst. value 00h read value 00h ? dmausb channel 0-3 upper address counter value. address will only count by 2. ? reading this register will return the active address value when the last usback occurred. note : this register is double buffered. writing to this location twice will load the active register as well as the buffer register. upon a block limit interrupt, the buffer value will be activated therefor a new buffered value should be written to this register. dmausb0cnthi 01ff81ca-cb dmausb1cnthi 01ff81d0-d1 dmausb2cnthi 01ff81d6-d7 dmausb3cnthi 01ff81dc-dd
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-87 address:ch4csbs bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dmausb transfer block size reg. (dmausbblocksize ) usb channel enable = 1 stop at block upper six bits of the block size counter rst. value 00h read value 00h address:ch4csbs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dmausbtransfer block size reg. (dmausbblocksize ) low byte value for usb memory block size counter rst. value 00h read value 00h block size data written to this register will be placed into the inactive block size register. this register will become active once the prior block has completed (usb irq). reading this register will return the block size value when the last usback occurred. writing to this will initialize the logical channel. therefore, when setting up a logical channel, this register should be written to last. note : this register is double buffered. writing to this location twice will load the active register as well as the buffer register. upon a block limit interrupt, the buffer value will be activated therefor a new buffered value should be written to this register. ? dma usb channel block size limit counter dmausb0 blksiz 01ff81cc-cd dmausb1 blksiz 01ff81d2-d3 dmausb2 blksiz 01ff81d8-d9 dmausb3 blksiz 01ff81de-df bits [13:0] dmausb memory block size the block size of dma channel can range from 1 ? 16383 dma transfers. the block size counter will decrement regardless of the dma address counter?s activity. the block size register content is 0000h when the block size limit is reached. when the block size reaches its limit, an irq will be generated upon the next channel ack. writing to this register will clear the irq. bit 14 note : when this bit is set, the dma channel will disable it?s self until a new block size is entered. if this bit is 0, when a block limit is reached the next block size will be downloaded into the counter along with the next dma address and transfers will continue within the new block. upon the next channel ack, an irq will be generated. bit 15: this bit must be set at all times to enable the channel and is not part of the double buffering process.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-88 conexant 100723a address:ch1cscntl bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma 1 configuration (dma0config) $xx8183 dmaack1 delay-off 0=normal 1=delay ? siuclk cycle not used not used not used not used not used not used not used rst. value 00h read value 00h address:ch1cscntl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma 1 configuration (dma0config) $xx8182 read = 1 write = 0 enable 0 = disable 1 = enable not used not used not used not used not used count by 0=byte 1=halfword rst. value 00h read value 00h bit 0: sets byte or halfword data access to match external devices. bit 6: this bit controls the channel enable bit 7: this bit controls the external data direction bit 15: setting this bit to a 1 will extend the external dmaack ? siuclk cycle so that it may be used as a chip select. address:ch2cscnt bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma 2 configuration (dma2config) $xx81b3 dmaack2 delay-off 0 = normal 1 = delay half siuclk cycle (write only) not used not used not used not used not used brb to memory, data transfer (write only) byte mode = 0 ? word mode = 1 rst. value 00h read value 00h address:ch2cscnt bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma 2 configuration (dma2config) $xx81b2 read = 1 write = 0 requested device 0=bit rot. 1= ext mem 0 = inc 1 = dec count by 1024 count by 512 count by 256 count by 2 count by 1 rst. value 00h read value 00h dma channel 2 address jump, increment, and decrement control. the count by control bits allows the user to select how the address is progressed after each dma access. only one count by bit can be set at a time. if there are no count by control bits selected the address will remain fixed. bit 15: if dmaack2 is used as a select signal (like a chip select), the extended dmaack2 may be needed. this ?dmaack2 delay-off? bit needs to be set to ?1? for extending dmaack2 half siuclk cycle. bit 9: this bit controls the source of the dma request. if this bit is set to 0 and bit 6 is set to 0, a external support chip must be used to provide an external dma request for transferring printer data. if an external device is not used, the bit rotation block can directly transfer print data to memory. to operate in this mode bit 9 should be set to 1, bit 6 set to 0, and bit 7 set to 0 for dma writes to memory. if bit 6 is set to 1, bit 9 must be set to 0.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-89 bit 8: if the bit rotation block is selected (bit 6 = 0), and the external data bus for the print asic is byte wide, this bit needs to be ?0?. if the bit rotation block is selected (bit 6 = 0), and the external data bus for the print asic is halfword wide, this bit needs to be ?1?. if external memory is selected (bit 6 = 1), the external bus data width for the print asic and external memory need to be matched (this bit is not used). bit 7: control bit definition is with reference to the dma requested device and controls the read/write signals during the dma cycle. if it is set to write, the write strobe will be active during the dma cycle. bit 6: if the bit rotation block is selected ( bit 6 = 0), the dma request will be held off when the bit rotation block output register is not ready. the asic output bus drivers will be disabled during external dma request write (bit 6 = 1 and bit 7 = 0). bit 5: controls the address count direction performed after each dma cycle. bit 4-0: these bits control how the address registers will count after each dma cycle. note: if byte mode is set, the count by 1 should be set. note : requests to this channel are delayed by two clocks for synchronization. address:ch2csbs bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma 2 transfer block size reg. (dma2blocksize) $xx81b5 channel 2 enable = 1 not used not used not used not used not used upper two bits of the block size counter rst. value 00h read value 00h address:ch2csbs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma2 transfer block size low byte reg. (dma2blocksizelo) $xx81b4 low byte value for the external dma block size counter rst. value 00h read value 00h ? dma channel 2 block size limit counter ? block size of dma channel 2 (halfwords) ? unlimited block size (block size = ): bit[7:0] of the dma2blocksize register = 00h bit[9:8] of the dma2blocksize register = 00b. ? limited block size (block size = 1 - 1023) ? the block size counter will decrement regardless of the dma address counter?s activity. the block size register content is 0000h when the block size limit is reached. ? please see the operation description of dma2blksize and dma2bufblksize registers below (in the dma2bufblksize register section). ? writing to this register will also clear the dma channel 2 interrupt. bit 15: channel 2 enable is cleared when the block size limit is reached, and must be set, (enabled) after a new block size is entered. the block size can only be written into the dma2blksize register when this bit is 0.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-90 conexant 100723a address:ch2csbbs bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma ch2 buffered transfer block size reg. (dma2bfblocksize) $xx81b7 ch2 enable = 1 not used not used not used not used not used upper two bits of the block size counter rst. value 00h read value 00h address:ch2csbbs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma ch2 buffered transfer block size low byte reg. (dma2bfblocksizelo) $xx81b6 low byte value for the external dma block size counter rst. value 00h read value 00h ? dma channel 2 buffered block size limit counter ? block size of dma channel 2 (1/2 words) ? unlimited block size (block size = ): bit[7:0] of the dma2blocksize register = 00h bit[9:8] of the dma2blocksize register = 00b. ? limited block size (block size = 1 - 1023) ? the first transfer block size and the starting address must be set up in the dma2blksize and dma2 address registers. the second transfer block size and the starting address must be set up in the dma2bufblksize and dma2 buffered address registers. then, firmware only needs to update the dma2bufblksize and dma2 buffered address registers when the dma channel 2 interrupt occurs. this allows preloading of the next block size and starting address before the dma operation for the current block has completed. ? the buffered block size will be down loaded into the block size counter when the current block size is reached and a new value has been written into this buffered block size register. writing to this register will also clear the dma channel 2 interrupt. ? the block size can be written into the dma2bufblksize register only when the value of bit 15 in the dma2blksize register is set to 0. address: chcsbl[2] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma ch2 buffered low counter (dma2cntblo) $xx818d dmab2 addr. bit 15 dmab2 addr. bit 14 dmab2 addr. bit 13 dmab2 addr. bit 12 dmab2 addr. bit 11 dmab2 addr. bit 10 dmab2 addr. bit 9 dmab2 addr. bit 8 rst. value 00h read value 00h address: chcsbl[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma ch2 buffered low counter (dma2cntblo) $xx818c dmab2 addr. bit 7 dmab2 addr. bit 6 dmab2 addr. bit 5 dmab2 addr. bit 4 dmab2 addr. bit 3 dmab2 addr. bit 2 dmab2 addr. bit 1 dmab2 addr. bit 0 rst. value 00h read value 00h ? dma channel 2 lower buffered address counter value ? the buffered address counter value will be down loaded into the address counter when the current block size is reached and a new value has been written into this register.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-91 address: chcsbh[2] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma ch2 buffered hi counter (dma2cntbhi) $xx818f not used not used not used not used not used not used not used not used rst. value 00h read value 00h address:chcsbh[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma ch2 buffered hi counter (dma2cntbhi) $xx818e dmab2 addr. bit 23 dmab2 addr. bit 22 dmab2 addr. bit 21 dmab2 addr. bit 20 dmab2 addr. bit 19 dmab2 addr. bit 18 dmab2 addr. bit 17 dmab2 addr. bit 16 rst. value 00h read value 00h ? dma channel 2 upper buffered address counter value ? the buffered address counter value will be down loaded into the address counter when the current block size is reached and a new value has been written into the buffered block size register. address:ch5csbs bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma5 transfer block size reg. (dma4blocksize) $xx81bb channel 5 enable = 1 not used upper six bits of the block size counter rst. value 00h read value 00h address:ch5csbs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma5transfer block size reg. (dma4blocksize) $xx81ba low byte value for the pio to memory block size counter rst. value 00h read value 00h ? dma channel 5 block size limit counter ? block size of dma channel 5 (bytes) ? unlimited block size (block size = ): bit[13:0] of the dma5blocksize register = 0000h limited block size (block size = 1 - 16380) ? the block size counter will increment regardless of the dma address counter?s activity bit 15: channel 5 enable is cleared when the block size limit is reached, and must be set, (enabled) after a new block size is entered. this bit is also inverted and sent to the pio as maxdmacnt. the new block size can only be written when this bit is 0.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-92 conexant 100723a address:ch9csbs bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma9 transfer block size reg. (dma9blocksize) $xx81bf channel 9 enable = 1 not used not used not used upper four bits of the block size counter rst. value 00h read value 00h address:ch9csbs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma9transfer block size reg. (dma9blocksize) $xx81be low byte value for the bi-level resolution conversion logic block size counter rst. value 00h read value 00h ? dma channel 9 block size limit counter ? block size of dma channel 9 (bytes) ? unlimited block size (block size = ): bit[11:0] of the dma9blocksize register = 000h limited block size (block size = 1 - 4095) ? the block size counter will decrement regardless of the dma address counter?s activity. the block size register content is 0000h when the block size limit is reached. ? writing to this register will also clear the bi-level resolution conversion interrupt. bit 15: channel 9 enable is cleared when the block size limit is reached, and must be set, (enabled) after a new block size is entered. the new block size can only be written when this bit is 0. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma6/10 throttle (dma6/10throttle) $01ff81bd throttle ch. select 0= ch. 6 1= ch. 10 throttle value bit 14 throttle value bit 13 throttle value bit 12 throttle value bit 11 throttle value bit 10 throttle value bit 9 throttle value bit 8 rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma6/10 throttle (dma6/10throttle) $01ff81bc throttle value bit 7 throttle value bit 6 throttle value bit 5 throttle value bit 4 throttle value bit 3 throttle value bit 2 throttle value bit 1 throttle value bit 0 rst. value 00h read value 00h ? throttle value (tv) = 1-32767 (tv= 0; disables throttle function) throttle value (tv) allows 1 dma access every ?tv*siuclk? time period. ? dma channel 6 or 10 throttle control: this register is loadable while the dma is active. write to this register will reset the throttle timer.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 4-93 address:ch10csbs bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma10 transfer block size reg. (dma10blocksize) $xx81c1 channel 10 enable = 1 not used not used not used upper four bits of the block size counter rst. value 00h read value 00h address:ch10csbs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma10transfer block size reg. (dma10blocksize) $xx81c0 low byte value for the pio to memory block size counter rst. value 00h read value 00h ? dma channel 10 block size limit counter ? block size of dma channel 10 (bytes) ? unlimited block size (block size = ): bit[11:0] of the dma10blocksize register = 000h ? limited block size (block size = 1 - 4095) ? the block size counter will decrement regardless of the dma address counter?s activity. the block size register content is 0001h when the block size limit is reached. ? writing to this register will also clear the dma channel 10 interrupt. bit 15: channel 10 enable is cleared when the block size limit is reached, and must be set, (enabled) after a new block size is entered. the new block size can only be written when this bit is 0. address: csincconf bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma increment configuration (dmaincconfig) $xx81c3 not used usb3 inc = 0 dec = 1 usb2 inc = 0 dec = 1 usb1 inc = 0 dec = 1 usb0 inc = 0 dec = 1 dma 12 inc = 0 dec = 1 dma 11 inc = 0 dec = 1 dma 10 inc = 0 dec = 1 rst. value 00h read value 00h address: csincconf bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma increment configuration (dmaincconfig) $xx81c2 dma 9 inc = 0 dec = 1 dma 8 inc = 0 dec = 1 dma 7 inc = 0 dec = 1 dma 6 inc = 0 dec = 1 dma 5 inc = 0 dec = 1 dma 4 inc = 0 dec = 1 dma 1 inc = 0 dec = 1 not used rst. value 00h read value 00h ? dma address increment configuration. the increment configuration control bit allows the user to select where the dma channel increments or decrements after each access.
MFC2000 multifunctional peripheral controller 2000 hardware description 4-94 conexant 100723a address: cscontenb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma count enable (dmacntconfig) $xx81c5 not used not used not used not used not used dma 12 count enable dma 11 count enable dma 10 count enable rst. value 07h read value 07h address:cscontenb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma count enable (dmacntconfig) $xx81c4 dma 9 count enable dma 8 count enable dma 7 count enable dma 6 count enable dma 5 count enable dma 4 count enable dma 1 count enable not used rst. value feh read value feh ? dma address count enable control. the count enable control bit allows the user to enable address count after each dma access. if the count enable control bit is not set the address will remain fixed. address: cscontenb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: dma endian control (dmaendian) $xx81c7 not used not used not used dma 12 endian control dma 11 endian control dma 10 endian control dma 9 endian control dma 8 endian control rst. value 00h read value 00h address:cscontenb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: dma endian control (dmaendian) $xx81c6 dma 7 endian control dma 6 endian control dma 5 endian control dma 4 endian control dma 3 endian control dma 2 endian control dma 1 endian control not used rst. value 00h read value 00h ? dma address endian control. if the endian control bit is set to a 1, the data structure will be changed between the little endian mode and the big endian mode. the current data structure the changed data structure address 00: byte 0 !" address 11: byte 0 address 01: byte 1 !" address 10: byte 1 address 02: byte 2 !" address 01: byte 2 address 03: byte 3 !" address 00: byte 3 for dma 1 (the external dma channel) and dma 2 (programmed as external dma channel), this endian control can?t be used for accessing external memory (the associated bit needs to be set to 0). if the external i/o device tries to get/put data from/to internal memory or registers, this endian control can be used with no problem. for example, if the external print asic tries to get data from the internal bit rotation block through dma 2, this endian control can be used with no problem. if the external print asic tries to get data from the external memory through dma 2, this endian control can?t be used. in this case, the right endian structure should be prepared when the data is put into the external memory through the other process and dma channels.
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multifunctional peripheral controller 2000 MFC2000 100723a conexant 5-1 5. reset logic/battery backup/watch dog timer 5.1 reset logic/battery backup the MFC2000 has two power resets, battery power reset and prime power reset. the battery power reset is the primary reset used to initialize battery-powered logic when battery power is first applied. prime power reset initializes all non-battery powered logic whenever system power is applied. a third reset is generated by the watchdog timer or by the resetn pin. the major logic blocks and associated MFC2000 signals are illustrated in figure 5-1. note: reset logic operation requires use of the rtc crystal (connected to xin and xout).
MFC2000 multifunctional peripheral controller 2000 hardware description 5-2 conexant 100723a prime power battery power power up delay 2 & retime to local_clk resn resetn reset sync sysclk power up delay 1 fax timing block mclk for arm7 cpu local_clk siuclk divider xout pwrdwn_padn clock enable sysirq routine sysirq for power down lockout logic dram refresh control tristate control batrstn clear lockout battery refresh inactive vdd refresh enable to battery register reset cs0n rasn[1:0] cason[1:0] casen[1:0] dwrn battrtc_resn pwrdwn select logic ext_pdsel pwrdwn figure 5-1. power reset block diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 5-3 0 1 1 0 ext_pdsel_padn int_pwrdwn_sel sia_pwr_down1 sia_pwr_down2 pwrdwn_padn figure 5-2. power-down select logic 5.1.1 battery power reset battery power reset is generated when batrstn (as shown at lower left in figure 5-1) is driven low, and initializes the MFC2000 when battery power is first applied, as well as forcing a prime power reset if v dd is present. as long as battery power is maintained, there is no need to reactivate this reset. if the system design does not utilize the MFC2000's battery power features, this reset should be tied to pwrdwnn and be activated upon system power initialization. battery backup system requirements are undefined when battery power is first applied. consequently, batrstn disables the battery backup control for dram and disables sram by resetting the backupconfig register, and inhibits cpu access to this register via the (internal) lockout signal. the disabling of battery backup controls tri- states the associated output control signals (i.e., cs[0]n for sram, and cason[1:0]n, casen[1:0], rasn[1:0], and dwrn for dram, as shown at lower right in figure 5-1. note: the proper off-state logic level for battery backed-up devices external to the MFC2000 must be maintained by external pull-up/pull-down resistors on the appropriate MFC2000 pins. batrstn has a schmitt trigger input buffer to allow the use of an external rc circuit to generate a reset. 5.1.2 prime power reset prime power reset occurs when pwrdwnn (shown at upper left in figure 5-1) is driven low while prime power is applied. there are two prime power reset operating modes, one for v dd power on and one for v dd power off.
MFC2000 multifunctional peripheral controller 2000 hardware description 5-4 conexant 100723a v dd power on v dd power on occurs when v dd power reaches it's normal operating level and pwrdwnn is driven high, resulting in ?power-up delay 1? (pud1) initiation (shown at upper left in figure 5-1). pud1 has a duration of one or two reset clocks (internal signal), depending on when pwrdwnn is driven high with respect to the reset clock rising edge. once pud1 times out, the internal signal battrtc_resn is released. the internal reset clock signal (resn) duration is equal to approximately 125 ms for xout = 32.768 khz. reset clock = xout/4096 ?power-up delay 2? (pud2) is a time delay whose duration is approximately 8 periods of siuclk (6 siuclk periods + time for retiming to auxclk). this delay allows cpu pre-operation initialization. once pud2 times out, resetn gets resynchronized to auxclk and then, changes from an active low state to a high impedance state. after resetn goes to the high impedance state, resn goes high approximately after 8 periods of siuclk. after the internal resn signal goes high, all internal logic gets reset and the battery back-up lockout is removed on the next xout rising edge. v dd power off v dd power off occurs when pwrdwnn is driven low while v dd is at a normal operating level. as an MFC2000 battery backed up feature, pwrdwnn has been designed to work with an early warning power loss detector. this allows the firmware to backup sensitive variables, and the MFC2000 to protect nonvolatile data from erroneous logic operations while prime power transitions through low voltage levels (i.e., < 3.135v). when pwrdwnn is driven low, an sysirq is issued to the cpu, and the cpu sysirq routine then performs necessary system house cleaning tasks before power loss. the final sysirq routine task is to write to the lockenn register, which enables the battery lockout logic. the battery lockout logic forces an immediate lockout if battery dram operation is not enabled. if dram operation is enabled, the battery lockout logic waits for the absence of a v dd refresh cycle before performing the lockout. while in lockout, battery refresh mode commences, battrtc_resn becomes active, and the MFC2000 is inactive until the next v dd power on cycle. time-out logic for the power-down lockout there is a 1-2 second time-out on lockenn, if power down goes low enough to get latched into the battery logic, but a lockenn doesn?t get generated by software. this will guarantee that a reset will occur if power down ever gets set and software doesn?t set lockenn so that a reset gets generated. there are two status bits to the backup configuration register. bit 12 indicates that a battery reset (from the pin batrstn) has been detected. bit 11 indicates that a lock enable has occurred and was caused by the time-out circuitry or a software write. to reset either of these bits a 1 must be written to the appropriate bit.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 5-5 5.1.3 external reset (resetn) and watchdog reset a driver on the ampfc's resetn pin provides a reset signal to external devices whenever the internal battrtc_resn or watchdog reset is active (low). this pin also includes an input driver that allows external control circuitry to reset the cpu and all v dd powered registers (including a power-down sysirq condition). the external resetn and internal resn are also activated when the watchdog timer times out (refer to the watchdog timer section that follows). an externally generated reset does not affect the battery powered registers nor dram refresh operation. [caution] don?t drive the resetn pin ?high? from external. only drive the resetn pin ?low? to generate the reset from external and don?t drive the resetn pin when external reset is not needed. 5.1.4 power reset timing diagram the battery and v dd power on reset timing is illustrated in figure 5-1. the first event shown is the battery voltage and lockout rising together as battery voltage is applied, followed by batrstn going high, and the start up of xout. on the second falling edge of reset clock after v dd has been applied and pwrdwnn has been driven high, battrtc_resn goes high and approximately eight siuclks are counted as power-up delay 2. at the completion of eight siuclks, battery lockout is removed allowing access to the backupconfig register. internal clock on pwrdwnn power up delay 1 (125-250ms) power up delay 2 (8 siuclks) 8 siuclks) (internal) siuclk (internal) reset clock - 125ms battery voltage lockout batrstn vdd (internal) battrtc_resn resetn (internal) resn (internal) clock enable figure 5-3. power reset timing diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 5-6 conexant 100723a 5.1.5 power on/off sequence 5.1.5.1 power type +3.3v prime power signal ? connect to vdd pins on the MFC2000 chip to supply prime power to the MFC2000 die in the MFC2000 chip. +5v prime power signal ? connect to adva and advd pins on the MFC2000 chip to supply prime power to the adc die in the MFC2000 chip. ? connect to vgg pins on the MFC2000 chip to supply +5v prime power to all +5v tolerant pads in the MFC2000 chip. +3v battery power signal ? connect to the vbat pin on the MFC2000 chip to supply battery power to the battery backup rtc in the MFC2000 chip and external sram. ? connect to the vdram pin on the MFC2000 chip to supply battery power to the battery backup dram refresh logic in the MFC2000 chip and external dram. 5.1.5.2 prime power sequence it is recommended that +3.3v prime power signal is supplied first and then, supply +5v prime power signal for the prime power-on sequence. in other words, the voltage level of +5v prime power signal must be lower than the voltage level of +3.3v prime power signal before +3.3v prime power signal reaches the stable level. v +5 is turned off first and then, turn off v +3.3 for the prime power-off sequence. in other words, the voltage level of +5v prime power signal must be always lower than the voltage level of +3.3v prime power signal during the power-off sequence. the recommended connection between +5v prime power signal and vgg is shown: 1kohm .1uf +5v vgg figure 5-4. +5v prime power signal and vgg
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 5-7 5.1.6 register description battery backup and prime power reset registers name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default backup configuration register (backupconfig) $01ff8099 (not used) (not used) internal power down select battery reset flag lockout time-out flag sram enable 0 = disable 1 = enable bank 1 data interface size: 0 = 8-bit 1 = 16-bit bank 0 data interface size: 0 = 8-bit 1 = 16-bit rst. value xxx00000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default backup configuration register (backupconfig) $01ff8098 dram backup time 0 = no backup 1 = 1-2 days 2 = 2-3 days 3 = infinite days refresh rate 0 = normal 1 = slow oscillator speed 0 = 32.768 khz 1 = 65.536 khz bank 1 enable 0 = disable 1 = enable bank 0 enable 0 = disable 1 = enable bank 1 interleave enable 0 = non interleaved 1 = 2 way interleaved bank 0 interleave enable 0 = non interleave d 1 = 2 way interleave d rst. value 00h read value 00h register description: this register is set to all zeros when first powered up and is battery backed up with the rtc battery during power down. when a time out condition occurs, the rasn and casn signals are tristated. when prime power has returned from a power down sequence, the user will have to perform a checksum on the dram data to know if a time out has occurred since there is no indication that the dram battery has lost power. the user will have to wait 1ms before accessing the dram after prime power has returned. bits 15-14:not used bits 13: internal power down select 0 = pwrdwnn is generated by or-ing power_down1 with power_down2 1= pwrdwnn is generated by and-ing power_down1 with power_down2 note : power_down1 and power_down2 are output signals from the power-down detection circuit 1 and 2. bit12: battery reset flag this bit indicates that a batrstn occurred. to clear this bit, a 1 must be written to this bit. bit11: lockout time-out flag this bit indicates that a power down occurred, but no lockout was set with in the 1-2 second period. the lockout timer initiated the lockenn to create the lockout condition. once the lockout condition occurs, if the power down signal is high, the chip will come out of reset after a pud1 delay. to clear this bit, a 1 must be written to this bit. bit10: sram chip select enable this bit enables the sram chip select csn0. bit 9: bank 1 interface size this register defines whether the databus to the bank 1 drams is 8 bits wide or 16 bits wide. an 8-bit wide dram interface uses rasn[1] and cason[0]. a 16-bit wide non-interleaved dram interface uses rasn[1] and cason[1:0]. a 16-bit wide interleaved dram interface uses rasn[1], casen[1:0], and cason[1:0].
MFC2000 multifunctional peripheral controller 2000 hardware description 5-8 conexant 100723a bit 8: bank 0 interface size this register defines whether the databus to the bank 0 drams is 8 bits wide or 16 bits wide. an 8-bit wide dram interface uses rasn[0] and cason[0]. a 16-bit wide non-interleaved dram interface uses rasn[0] and cason[1:0]. a 16-bit wide interleaved dram interface uses rasn[0], casen[1:0], and cason[1:0]. bits 7-6: dram battery backup time these bits control the amount of time that the dram controller will spend refreshing the drams when in the battery backup mode. after reset when the cpu is being released to run, the cpu will not be able to write data to bits 7 and 6 of the backupconfiguration register immediately since the immediate write will not take effect. the cpu must wait at least one oscillator clock cycle before writing data into bits 7 and 6. bit 7 bit 6 battery backup duration: 0 0 no battery backup 0 1 1-2 days 1 0 2-3 days 1 1 infinite bit 5-4: dram refresh rate these bits are used to set up the dram refresh rate. see the following table: refresh speed: (bit 5) oscillator speed: (bit 4) refresh speed: description: 0 0 normal rtc crystal frequency = 32.768 khz, refresh clock = the crystal frequency= 32.768 khz, the refresh cycle time = 15.625 ms/1024 cycles. 0 1 fast rtc crystal frequency = 65.536 khz, refresh clock = the crystal frequency = 65.536 khz, refresh cycle time = 7.8125 ms/1024 cycles. 1 0 slow rtc crystal frequency = 32.768 khz, refresh clock = the crystal frequency/8 = 4.096 khz refresh cycle time = 125 ms/1024 cycles. 1 1 slow rtc crystal frequency = 65.536 khz, refresh clock = the crystal frequency/16 = 4.096 khz refresh cycle time = 125 ms/1024 cycles. bits 3: bank 1 enable this bit controls whether or not the bank 1 drams will be enabled. the enable signal will allow cas before ras refresh to occur based on the non-interleave or interleave setting. if the bank setting indicates a non-interleaved mode, rasn[1] and cason[0] (8-bit mode) or cason[1:0] (16-bit mode) will refresh the dram. if the bank setting indicates an interleaved mode, rasn[1], cason[1:0] and casen[1:0] will refresh the dram. dwrn will be high during refresh. casen[1:0] will be tristated if bank 0 is in non-interleaved mode. if this bit is set to a zero, rasn[1] will be tristated. default disabled.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 5-9 bit 2: bank 0 enable this bit controls whether or not the bank 0 drams will be enabled. the enable signal will allow cas before ras refresh to occur based on the non-interleave or interleave setting. if the bank setting indicates a non-interleaved mode, rasn[0] and cason[0] (8-bit mode) or cason[1:0] (16-bit mode) will refresh the dram. if the bank setting indicates an interleaved mode, rasn[0], cason[1:0] and casen[1:0] will refresh the dram. dwrn will be high during refresh. casen[1:0] will be tristated if bank 1 is in non-interleaved mode. if this bit is set to a zero, rasn[0] will be tristated. default disabled. bit 1: bank 1 interleave enable this register defines whether the bank 1 drams are to be accessed using 2-way interleave or non-interleaved access. 2-way interleaved access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface size bit for bank 1 is not used by the dram controller in the interleave mode, but is used by the siu to output the data correctly). bit 0: bank 0 interleave enable this register defines whether the bank 0 drams are to be accessed using 2-way interleave or non-interleaved access. 2-way interleaved access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface size bit for bank 1 is not used by the dram controller in the interleave mode, but is used by the siu to output the data correctly). address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default lock enable (lockenn) 01ff80a1(dw) a dummy write to the lock enable register will enable the battery/prime power lockout sequence for a power down condition. rst. value xxh read value xxh address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lock enable (lockenn) 01ff80a0 (dw) a dummy write to the lock enable register will enable the battery/prime power lockout sequence for a power down condition. rst. value xxh read value xxh ? a write to this register enables the battery power lockout sequence for a power down condition. lockout can only be cleared by resn. ? this is not a battery backed-up register.
MFC2000 multifunctional peripheral controller 2000 hardware description 5-10 conexant 100723a 5.1.7 power down detection the power down detection circuit was only external for the mfc1000 chip. the pwrdwnn input signal to mfc1000 is the output of the external power down detection circuit. the MFC2000 has two internal power down detectors. the pwrdwnn is configurable either from internal power down detectors or from external power down detector. the ext_pwrdwn_seln is used to select internal or external power down detector. the external power down detector is selected when the ext_pwrdwn_seln pin is low. if the internal power detectors are selected, the combination of two power down detector can be further selected through the internal register. the purpose of having internal power down detector is to automatically generate reset after voltage drop on the power supply without having external power down detector. the power supply voltage is compared with internally generated threshold voltages. in order to prevent erratic resets, the comparator is designed with hysteresis feature. during the power up, the output of the comparator will be low when the power supply voltage is at least v on . then as the voltage continues to increase and becomes larger than v on , the comparator output will be high. if at any time, the supply voltage drops below the threshold voltage level of v off , then the comparator output will be low. power1 + pwr_down1 power2 + voltage detector pwr_down2 reference voltage figure 5-5. internal power detection output voltage (v) adga input voltage (v) v hys v off adva [sia2k-comp-tf.vcd] figure 5-6. figure caption required
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 5-11 voltage threshold margin v off tadcref 30 mv v hys 20 mv 2 mv note : the output voltage to represent logic 0 must be guaranteed to be at adga (typically adga = gnd = 0v). the input resistance to the voltage detector is specified as follows: min r in input resistance 10 m ? a voltage divider circuit will be used externally in order to obtain the desired voltage to monitor the power. mfc2k voltage detector power1 5v or 3.3v r1 r2 power_down1 adva r in figure 5-7. voltage divider circuit 5.2 watchdog timer the watchdog timer is intended to guard against firmware lockup on the part of either executive-controlled background tasks or interrupt-driven tasks, and can only be enabled by a sequence of events under control of the watchdog control logic. once the watchdog timer has been enabled, it can not be disabled (inactivated) unless a system reset occurs. the watchdog timer block diagram is provided in figure 5-8, and the watc hdog time-out timing diagram is provided in figure 5-9. the watchdog timer is enabled by the following sequence of events, which must occur in the order described. 1. write the value of the desired time-out interval to the watchdog interval register. the first write to this register disables subsequent writes, and enables the next event in the enable sequence. 2. write $0f followed by $f0 to the watchdogenretrigger register. the data written to this register must be in the order specified or it is ignored. 3. after the operations are completed, the value in the watchdog interval register is loaded into the time-out down counter.
MFC2000 multifunctional peripheral controller 2000 hardware description 5-12 conexant 100723a 4. as soon as the watchdog timer is enabled, the time-out down counter begins counting. the time-out down counter is decremented based on a 1 ms pulse which is derived from (125 s prescaler period /8); the count occurs on the rising edge of siuclk. after the time-out down counter reaches 'zero', the (internal) watchdog reset signal becomes active at the next 1 ms pulse. the watchdog reset immediately activates the internal resn and external resetn signals. these resets are deactivated when the power up delay 2 timer times out (i.e., 8 siuclk's). in order to prevent the watchdog timer from timing-out and generating a reset pulse, it must be retriggered by writing $0f followed by $f0 to the watchdogenretrigger register. this action causes the value in the watchdoginterval register to be re-loaded into the time-out down counter. note: the 125us prescaler must be initialized before activating the watchdog timer. block 1, 2, 3, 4, and 5 resetn 1ms pulse siuclk data bus watchdog timer control 2 watchdog enretrigger register 3 watchdog reset generator 4 time-out down counter 5 data bus watchdog interval register 1 wdre s figure 5-8. watchdog timer block diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 5-13 0 n-1 1ms (n-1)ms 1ms t1msci wdres counter enable siuclk figure 5-9. watchdog time-out timing diagram 5.2.1 watchdog timer registers address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: watchdog enable retrig. (watchdogenretrigger) 01ff8041 (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: watchdog enable retrig. (watchdogenretrigger) 01ff8040 (w) writing 0fh followed by f0h to this register after setting the watchdog interval register will enable the watchdog timer. (the 125 sprescaler must be initialized before activating the watchdog timer.) always reads back ?00h?. rst. value 00h read value 00h
MFC2000 multifunctional peripheral controller 2000 hardware description 5-14 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: watchdog interval (watchdoginterval) 01ff8043 (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: watchdog interval (watchdoginterval) 01ff8042 watchdog interval (n = 0-255) (n*1ms) rst. value 00h read value 00h ? once enabled, the watchdog timer can only be disabled by reset. ? on reset, the watchdog timer is disabled until it is enabled by writing to the watchdoginterval register followed by writing $0f and $f0 to the watchdogenretrigger register. ? the basic watchdog time-out unit (1 ms) is based on the internal 125 sec timer. therefore, the 125sprescaler and msintperiod registers (used to activate the timer) must be set in order to operate the watchdog timer. ? the accuracy of the time-out period is equal to the accuracy of the 125 sec timer with an additional error of up to 1 msec (i.e., the amount of error is dependent on the relationship of the trigger point to the internal 1 msec timer). ? if n is programmed into the watchdoginterval register, the watchdog timer time-out period is "n * 1 ms" (n = 0 - 255). ? reading the address of the watchdoginterval register returns the value of n that was programmed into the watchdoginterval register. ? the following conditions do not enable the watchdog timer: only the first write to the watchdoginterval register is valid. the subsequent writes to this register are ignored. any other data written to the watchdogenretrigger register between the times $0f and $f0 are written is ignored. once enabled, the watchdog timer is retriggered on the writing of alternate $0f and $f0. (writing of any other data, and the writing of repetitive $0f or $f0 is ignored.)
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multifunctional peripheral controller 2000 MFC2000 100723a conexant 6-1 6. fax timing control interface 6.1 pll 6.1.1 description the MFC2000 is an asic that provides multifunctional control for color fax, color scan and color printing. the asic includes an arm microprocessor running at 30 mhz, 37.5 mhz or 40 mhz and a countach imaging dsp running at 100 mhz or 85.7 mhz. additionally, the asic also supports the usb interface running at 48 mhz and the auxclk at 10 mhz. the pll for the asic is designed to provide all the above frequencies in six operating modes based on the combination of arm frequency select and countach imaging dsp frequency select. the six operating modes are defined in the following table. 6.1.2 frequency requirement the frequencies for the six operation modes are defined as follows: table 6-1. operation mode frequencies clkconfig[1:0] clkconfig[2] arm (siuclk) countach usb auxclk 00 1 30 mhz 85.7 mhz 48 mhz 10 mhz 01 1 37.5 mhz 85.7 mhz 48 mhz 10 mhz 10 1 40 mhz 85.7 mhz 48 mhz 10 mhz 00 0 30 mhz 100 mhz 48 mhz 10 mhz 01 0 37.5 mhz 100 mhz 48 mhz 10 mhz 10 0 40 mhz 100 mhz 48 mhz 10 mhz 11 don?t care the MFC2000 can only operate in one mode at a time. the mode selection is made during the reset through clock configuration pins (clkconfig[2:0]). the input reference frequency is 28.224 mhz, which is generated by a crystal oscillator pad. 28.224mhz is also used for the internal p80 modem dsp.
MFC2000 multifunctional peripheral controller 2000 hardware description 6-2 conexant 100723a 6.2 fax timing logic the fax timing logic block generates all of the time bases needed by the MFC2000. the fax timing logic block diagram is provided in figure 6-1. (1) i_lclphi is only used internally to indicate the siuclk cycle before the last siuclk cycle in one iclk time period. (2) ihs_lclphi is only used internally to indicate the siuclk cycle before the last siuclk cycle in one ihsclk time period. (3) iclk is the base clock for internal peripherals and is only used internally to synchronize all the internal logic. the frequency of iclk must be equal to or less than 10mhz. iclk duty cycle is 33% when iclk = siuclk/3. (4) ihsclk is the high speed base clock for the pio and bit rotation blocks and is only used internally to synchronize all the internal logic. the frequency of ihsclk must be equal to or less than 20mhz. (5) auxclk has the same frequency as iclk and is output to the external world through a pin. auxclk is used to synchronize external peripherals. auxclk duty cycle is always 50% no matter what is the relationship between iclk and siuclk. (6) mmclk is the base clock for the motor control logic. (7) tim_8ms is used by the pio block. (8) tim_1ms is the base clock for the the watchdog timer. (9) tim_msint is used to synchronize the scanning and motor stepping. (10) tim_1ms/2msirq is used to generate an interrupt every 1ms or 2ms (selectable). the actual period of the 1msirq = 1.00708 ms and 2msirq = 2.01416ms notes: (from rtc) mmclk onemsclk tim_1ms/2msirq siuclk divide by 8 divide by b b= [iclk period]+1 b is from 2 to 4 iclkand auxclk divide by c c= [prescaler]+1 c is from 1 to 256 divide by d d= [msint perild]+1 d is from 1 to 64 watchdog timing generator tim_msint 1ms/2msirq generator tim_1ms_siuclk divide by a ihs_lclphi ihsclk a= [ihsclk period]+1 a is from 1 to 2 i_lclphi tim_125us_siuclk ihsck1x_seln divide by 8 tim_8ms tim_125us_iclk figure 6-1. fax timing control logic block diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 6-3 6.3 MFC2000 timing chain the MFC2000 timing chain is illustrated in figure 6-2. iclk (auxclk) divide by b siuclk divide by 8 divide by g divide by 8 divide by c a = [ihsclk period] + 1 divide by e divide by d about 1ms for watchdog timer d = [msint period] + 1 e = [ scan cycle] + 1 scan cycle divide by 2 divide by 8 divide by h g = [scandotscaler] +1 h = [scandotperiod] + 1 vc1pos, vc1neg scanbytes(2-512 bytes) clk1, clk1n clk2pos, clk2neg startpos, startneg adcsamplepos vc0pos, vc0neg 1ms/2msirq gen. 1ms/2msirq* onemsclk(from rtc) divide by f f = [ step clock ] + 1 stepclk for vertical print motor stepping and scan motor stepping mmclk b = [iclk period] + 1 divide by a c = [125us prescaler] + 1 ihsclk adclk on/off control adclk for adc die msint for scanning and motor stepping synchronization for tone generator divide by 8 125us synchronized to siuclk about 8ms for pio for watchdog timer and bell/rin g g enerator figure 6-2. MFC2000 timing chain
MFC2000 multifunctional peripheral controller 2000 hardware description 6-4 conexant 100723a 6.4 scan control timing in this example, the scan motor has the constant speed. the scan motor stepping is synchronized to the msint. the scan irq is used to disable motor stepping when we want to finish scanning. if the delay time for the scan motor is long enough, the last step will occur after the scan irq. then, we need to use the scan step irq (sstepirq) for disabling motor stepping. the detail description for the motor stepping is described in section 12. - load delay timer register for scan motor - load step timer register for scan motor - set stepping mode and dir for scan motor - load the initial step pattern - set scan motor mode for sm[3:0] - enable step - enable scan irq - set dma for line 1 - scan once (line 1) msint-0 tics step - disable step - set dma for line 3 - scan once (line 3) dela y time step time step time - enable scan video signals - set gpo mode for sm[3:0] disable scan irq scan irqs (last msint) step scan line 1 scan line 2 shift out line 1 step step - set dma for line 2 - scan once (line 2) step step scan line 3 shift out line 2 shift out line 3 figure 6-3. scan control timing
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 6-5 6.5 fax timing registers address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: 125 us prescaler (125usprescaler) 01ff8881 (not used) rst value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: 125 us prescaler (125usprescaler) 01ff8880 n (8 bits) as applied in the equation: (n+1)*(iclk period *8) rst value 00h read value 00h address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: iclk(auxclk) period (iclkperiod) 01ff8883 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: iclk(auxclk) period (iclkperiod) 01ff8882 (not used) (not used) (not used) (not used) (not used) ihsclk period iclk (auxclk) period iclk= siuclk/(iclkperiod + 1) rst value xxxxx111b read value 07h ihsclk = mclk/(ihsclkperiod + 1) address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: mechanical subsystem (ms) period (msintperiod) 01ff8885 (not used) (not used) (not used) rst value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: mechanical subsystem (ms) period (msintperiod) 01ff8884 2msirq select 0=1msirq 1=2msirq (not used) n (6 bits) as applied in the equation: (n+1)*125 us prescaler period) rst value 0x000000b read value 0x000000b on reset, the 125usprescaler, 1-ms timer, and msint counters are disabled. writing to the msintperiod register enables these timers and counters. in addition, the 125usprescaler must be set to the appropriate value in order for the watchdog and timing chains to operate correctly. if a new value is written into the msintperiod register while the msint counter is running, the new value is not loaded into the counter until it counts down to 0. 1ms/2msirq is a programmable interrupt source. if the ?2msirq select? bit (bit7) of the msintperiod register is set to 0, the interrupt is generated every 1ms (1.00708ms). if the ?2msirq select? bit (bit7) of the msintperiod register is set to 1 , the interrupt is generated every 2ms (2.01416ms).
MFC2000 multifunctional peripheral controller 2000 hardware description 6-6 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: interrupt clear (intclear) 01ff8887 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: interrupt clear (intclear) 01ff8886 (w) (not used) (not used) (not used) (not used) (not used) (not used) (not used) 1=clear 1ms/2msirq rst value xxxxxxx0b read value 00h
multifunctional peripheral controller 2000 MFC2000 100723a conexant 7-1 7. video/scanner controller the video/scanner controller consists of three main blocks: ? scanner controller ? industry standard two-wire serial programming interface ? video decoder interface the following diagram shows the block diagram of vsc. sensor video sensorctrl MFC2000 data and clock mux registers video/scan controller scan analog frontend msint counter & irq generator msintcy vsc_irq system interface vsc_adc_data[7:0] vsc_adc_start vsc_adc_stop vsc_adc_drdy vsc_adc_dclk two-wire serial interface video decoder chip led (s) ledctrl scanin video decoder interface siactrl clamp pga padc scanner controller figure 7-1. video/scanner controller block diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 7-2 conexant 100723a 7.1 scanner controller the function of scanner controller can be divided into three areas: 1. scanner sensor controller 2. scanner light controller 3. scan integrated analog controller pins related to scanner and external adc # scanner related sc_start[0] sc_ledctrl[0] sc_ledctrl[1]/sc_start[1] sc_ledctrl[2]/sc_start[2] sc_clk1/sc_clk2a gpio[0]/ext_clamp gpio[8]/sc_clk1/sc_clk2b gpio[15]/sc_clk1/sc_clk2c gpio[22]/eadc_sample/sc_clk2d ev_vd[5]/scaniaconfig[5] as gpo ev_vd[4]/scaniaconfig[4] as gpo ev_vd[3]/sample/clk2d ev_vd[2]/clk1/clk2c ev_vd[1]/clk1/clk2b ev_vd[0]/clamp # ext adc related 12-bit adc MFC2000 clock data[0] data[1] data[2] data[3] data[11:4] data[11:0] clk gpio[9]/ eadc_d[2] ev_vd[7:0]/ eadc_d[11:4] gpio[6]/ eadc_d[3] gpio[22]/ eadc_sample pm[0]/gpo[0]/spi_sid/ eadc_d[0] pm[1]/gpo[1]/spi_sic/ eadc_d[1] # related gpio configuration: configuration bit on gpioconfig2 ($01ff8832) ext_clamp on gpio[0] set bit 4 sc_clk1/2b on gpio[8] set bit 2 sc_clk1/2c on gpio[15] set bit 3 eadc_sample/sc_clk2d on gpio[22] set bit 6
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-3 7.1.1 function description features for scanner controller: ? supports wide variety of cis and linear ccd scanners (color or monochrome) ? supports up to 8192 (= 2 13 ) pixels/line ? programmable pulse width modulation for light control (up to 3 leds) ? programmable clamping signal (mode, delay, width, length) ? programmable sampling location (mode, location) ? supports external 12-bit adc with programmable latency and programmable data transfer position MFC2000 pin function alias sc_led0 ledctrl[0] scctrl[0] sc_st0 start[0] scctrl[1] sc_led0st1 ledctrl[1]/start[1] scctrl[2] sc_led2st2 ledctrl[2]/start[2] scctrl[3] sc_clk12a clk1/clk2a scctrl[4] sc_clk12b clk1/clk2b scctrl[5] sc_clk12c clk1/clk2c scctrl[6] a brief description of signal functionality: start sensor control signal which is only active at the beginning of a scan cycle in order to initiate the transfer of sensor data clk1 sensor control signal which toggles at pixel boundary; thus the frequency of this signal is half of pixel frequency clk2 sensor control signal whose rising and falling edges are programmable within a pixel period; thus the frequency of this signal is the same as the pixel frequency ledctrl light control signal which can either be the envelope or the modulation signal. the rising and falling edge of the envelope and the duty cycle of the modulation are programmable. 7.1.2 register description name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default scan control (scanctrl) $01ff8541 (not used) (not used) ledctrl[2] enable ledctrl[1] enable ledctrl[0] enable start[2] enable start[1] enable start[0] enable rst. value xx000000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default scan control (scanctrl) $01ff8540 (not used) (not used) (not used) (not used) (not used) (not used) (not used) scan once rst. value xxxxxxx0b read value 00h bit 13-11 ledctrl[2:0] enable this bit will be synchronized with ?cycle_start?, and it is not auto cleared. bit 10-8 start[2:0] enable this bit will be synchronized with ?cycle_start?, and it is not auto cleared. bit 0 scanonce writing 1 to this bit will initiate an image line scanning operation. this bit will be cleared automatically once the operation has been completed.
MFC2000 multifunctional peripheral controller 2000 hardware description 7-4 conexant 100723a name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default scan control status (scanctrlstat) $01ff8543 (not used) (not used) ledctrl[2] enable (read only) ledctrl[1] enable (read only) ledctrl[0] enable (read only) start[2] enable (read only) start[1] enable (read only) start[0] enable (read only) rst. value xx000000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default scan control status (scanctrlstat) $01ff8542 (not used) (not used) (not used) (not used) (not used) (not used) (not used) scan once (read only) rst. value xxxxxxx0b read value 00h this register is read only. the value written in scanctrl register will be transferred to this register at the beginning of scan cycle. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default vsc irq status (vscirqstatus) $01ff8545 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default vsc irq status (vscirqstatus) $01ff8544 (not used) (not used) (not used) (not used) (not used) (not used) spi irq msint irq rst. value xxxxxx00b read value 00h bit 1 spi irq this is the interrupt status which comes from spi block. the enable for this interrupt can be found in spi_config register. writing 1 to the status bit will clear the interrupt. bit 0 msint irq the scanenable must be set in order to have this interrupt active. the timing of this interrupt is programmable within a scan cycle. writing 1 to the status bit will clear the interrupt. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default vsc control (vscctrl) $01ff8547 shift enable[7:0] rst. value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default vsc control (vscctrl) $01ff8546 (not used) (not used) (not used) (not used) (not used) vsc on ev bus ihsclk period vsc mode rst. value xxxxxxx0b read value 01h
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-5 bit 15-8 shift enable[7:0] these bits are used to shift scanner controller signals by ? ihsclk. by default, all scanner controller signals are synchronized to the rising edge of ihsclk. by setting this bit, the corresponding scanner controller signal will be shifted by ? ihsclk, i.e., it will be synchronized to the falling edge of ihsclk. shiftenb[7]: to shift ?sample? signal shiftenb[6:1]: to shift ?scctrl[6:1]? signals shiftenb[0]: to shift ?clamp? signal bit 2 vsc on ev bus when this bit is set, the ?ev_vd[5:0]? bus will be turned into output with the following signals on the bus: ev_vd[5:0] output signals 5 scaniaconfig[5] as gpo 4 scaniaconfig[4] as gpo 3 sample/clk2d 2 clk1/clk2c 1 clk1/clk2b 0 clamp bit 1 ihsclk period 0: ihsclk period = sysclk period 1: ihsclk period = sysclk period/2) this bit determines the period of ihsclk (the primary clock of vsc). bit 0 vsc mode 0: scanner 1: video this mode will determine the source of data. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default scan cycle (scancycle) $01ff8891 (not used) (not used) (not used) msint irq location rst. value xxx11111h read value 1fh name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default scan cycle (scancycle) $01ff8890 (not used) (not used) (not used) scan cycle (n) msints per scan cycle = (n+1) rst. value xxx00000b read value 00h bits 12-8 msint irq location the value written here is double-bufferred. at the beginning of a scan cycle, the value will be transferred into another buffer which is compared to a scan cycle counter. if the value in the buffer matches the value in the counter, then an interrupt will be generated (if it is enabled) at the beginning of the count. bits 4-0 scan cycle (n, n = 0-31; msints per scan cycle = n+1) the value written here is double-buffered. at the beginning of a scan cycle, the value will be transferred into another buffer.
MFC2000 multifunctional peripheral controller 2000 hardware description 7-6 conexant 100723a notes 1. bits [4:0] of this register specify the number of msints (1-32) per scan cycle. total scan cycle period = [msint period * (scancycle register value + 1)]. 2. the transition from maximum count to 0 determines the start of a scan cycle. 3. reading bits [4:0] of this register returns the current scan cycle msint count. 4. this register must be set up prior to enabling the scan (i.e., setting the ?scanenable? bit in scanconfig register). name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default scan configuration (scanconfig) $01ff8893 msint irq enable scctrl[6] invert scctrl[5] invert scctrl[4] invert scctrl[3] invert scctrl[2] invert scctrl[1] invert scctrl[0] invert rst. value 00h read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default scan configuration (scanconfig) $01ff8892 (not used) external adc enable scctrl[6] select 0: clk1 1: clk2c scctrl[5] select 0: clk1 1: clk2b scctrl[4] select 0: clk1 1: clk2a scctrl[3] select 0: led2 1: start scctrl[2] select 0: led1 1: start scan enable rst. value xx000000b read value 00h bit 15 msint irq enable when this bit and scanenable bit are set, an interrupt will be generated based on the msint irq location defined in scancycle register. bit 14-8 scctrl[6:0] invert these bits are used to invert the polarity of the corresponding control signal. bits 6 external adc enable 0 = internal adc as the source of adc data 1 = external adc as the source of adc data bit 5-1 scctrl[6:0] select these bits are used to configure which scanner controller signals should be connected to the pins. bit 0 scan enable this bit must be set in order to activate the scanner controller logic. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default scan dot control (scandotctrl) $01ff8895 (not used) rst. value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default scan dot control (scandotctrl) $01ff8894 scan dot scaler value (0-15) n as used in the following equation: (n+1)*ihsclk scan dot period (1-15) n as used in the following equation: (n+1)*scandotscaler rst value 00h read value 00h bits 7-4 scandotscaler (n: 0-15), (n+1) * ihsclk period bits 3-0 scandotperiod (n: 1-15), (n+1) * scandotscaler note : scandotperiod = 0 is not allowed.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-7 name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default scan length (scanlength) $01ff8897 (not used) (not used) (not used) scanlength[12:8] rst. value xxx00000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default scan length (scanlength) $01ff8896 scanlength[7:0] rst. value 00h read value 00h bits 12-0 scanlength[12:0] this register specifies the number of valid pixels in one scan line. the amount of data stored in a line is scanlength * 2 bytes. each pixel is represented by 12-bit data, and it is stored in memory as 2 bytes of data. note : the internal pixel counter is 14-bit wide. the extra bit is used to match the maximum value of clamp delay and led edges. it is guaranteed that this counter will not roll-over once it reaches its maximum count. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default scan start delay (scanstartdelay) $01ff8899 (not used) (not used) (not used) delay [12:8] rst value xxx00000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default scan start delay (scanstartdelay) $01ff8898 delay [7:0] rst value 00h read value 00h bits 12-0 delay[12:0] 1.) the scanstartdelay register control the number of scan dots (pixels) that are to be skipped before valid scanner data is available. for example, if scanstartdelay = 1, the first valid scanner pixel is dot number 2, the second dot after the beginning of the start pulse. 2.) scanstart delay time = (delay[12:0] +1) * (scandotperiod). name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default start edges (startedges) $01ff889b (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default start edges (startedges) $01ff889a startneg value (0-15) start trailing edge position = (startneg+1)*(scandotscalerperiod) startpos value (0-15) start leading edge position = (startpos+1)*(scandotscalerperiod) rst value 00h read value 00h
MFC2000 multifunctional peripheral controller 2000 hardware description 7-8 conexant 100723a bits 7-4 startneg (0-15) startneg establishes the location of the start signal trailing edge. bits 3-0 startpos (0-15) startneg establishes the location of the start signal leading edge. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default start config (startconfig) $01ff889d guardband enable for scctrl[6] guardband enable for scctrl[5] guardband enable for scctrl[4] guardband[4:0] (in terms of pixel period) rst. value 00h read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default start config (startconfig) $01ff889c offset[3:0] (in terms of pixel period) length[3:0] (in terms of pixel period) rst. value xxxxxxx0b read value 00h bit 15-13 guardband enable for scctrl[6:4] when a guardband is enabled, then the corresponding control signal will not change (will be ?frozen?) for the duration specified by ?guardband? in bit 12-8. bit 12-8 guardband[4:0] some scanner requires a quiet period while start pulse is active. within this quiet period, only the start pulse will be toggling while other control signals are prevented from toggling. the duration of this period is determined by guardband * pixelperiod. bit 7-4 offset[3:0] the start pulse can be moved with respect to the start of scan cycle by this offset value which is expressed in terms of pixel period. bit 3-0 length[3:0] the duration of the start pulse is programmable according to this ?length? value. start pulse duration is [length + 1] * pixel_period name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default clk2a edges (clk2aedges) $01ff889f (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default clk2a edges (clk2aedges) $01ff889e clk2aneg value (0-15) clk2apos value (0-15) rst value 00h read value 00h bits 7-4 clk2aneg clk2aneg establishes the trailing edge of the clk2a signal relative to the start of each dot period, and is specified in scandotscaler clock periods. bits 3-0 clk2apos clk2apos establishes the leading edge of the clk2a signal relative to the start of each dot period, and is specified in scandotscaler clock periods.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-9 name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default clk2b edges (clk2bedges) $01ff88a1 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default clk2b edges (clk2bedges) $01ff88a0 clk2bneg value (0-15) clk2bpos value (0-15) rst value 00h read value 00h bits 7-4 clk2bneg clk2bneg establishes the trailing edge of the clk2b signal relative to the start of each dot period, and is specified in scandotscaler clock periods. bits 3-0 clk2bpos clk2bpos establishes the leading edge of the clk2b signal relative to the start of each dot period, and is specified in scandotscaler clock periods. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default clk2c edges (clk2cedges) $01ff88a3 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default clk2c edges (clk2cedges) $01ff88a2 clk2cneg value (0-15) clk2cpos value (0-15) rst value 00h read value 00h bits 7-4 clk2cneg clk2cneg establishes the trailing edge of the clk2c signal relative to the start of each dot period, and is specified in scandotscaler clock periods. bits 3-0 clk2cpos clk2cpos establishes the leading edge of the clk2c signal relative to the start of each dot period, and is specified in scandotscaler clock periods. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default adcsample configuration (adcsamplecfg) $01ff88a5 mode (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value 00xxxxxxb read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default adc sample configuration (adcsamplecfg) $01ff88a4 sampleneg value (0-15) samplepos value (0-15) rst value 00h read value 00h
MFC2000 multifunctional peripheral controller 2000 hardware description 7-10 conexant 100723a bits 15 mode this mode will only affect the number of sample pulses and not the number of sampled data to be stored into memory. 0 = sampling continuously as long as scanenable = 1 1 = sampling valid pixels only bits 7-4 sampleneg sampleneg establishes the trailing edge of the sample signal relative to the start of each dot period, and is specified in scandotscaler clock periods. bits 3-0 samplepos samplepos establishes the leading edge of the sample signal relative to the start of each dot period, and is specified in scandotscaler clock periods. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default clamp control (clampctrl) $01ff88a7 clamp mode internal clamp enable external clamp enable external clamp guardband enable external clamp invert (not used) (not used) (not used) rst value 0xxxxxxxb read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default clamp control (clampctrl) $01ff88a6 (not used) clamplengh[6:0] rst value x0000000b read value 00h bit 15 clampmode (1 = line?based, 0 = pixel?based) setting the clampmode bit causes line-based clamping to be used. clearing this bit causes pixel-based clamping to be used. for line?based clamping, the clamp signal is enabled for the number of dots specified in clamplength register, and can occur either before or after the valid pixel data, as selected by the clampdelay register. for pixel?based clamping, the clamp signal runs continuously throughout the entire scanline. bits 6-0 clamplength[6:0] this value specifies the number of pixels to be used for line?based clamping. note : both internal and external clamp share the same control signals for ?shift? and ?delay?. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default clamp delay (clampdelay) $01ff88a9 clamp position (not used) clamp delay[13:8] rst value 0x000000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default clamp delay (clampdelay) $01ff88a8 clamp delay [7:0] rst value 00h read value 00h
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-11 bit 15 clamp position (only valid for line?based clamping) setting the clampposition bit causes the clampdelay value to be applied from the start of the scanline (i.e., during the scanstartdelay time). clearing this bit causes the clampdelay value to be applied from the first valid pixel of the scanline (i.e., after the scanstartdelay has been accounted for). bits 13-0 clamp delay[13:0] (only valid for line?based clamping) the clampdelay register control the number of scan dots (pixels) that are to be skipped before enabling the clamp signal for the number of pixels specified in clamplength register. note : if clampposition bit = 0 and a new scanline is started before the clampdelay value has been satisfied, the clamp signal will not activate. the same is true if clampposition bit = 1 and the scanstartdelay value is less than the clampdelay value. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default clamp edges (clampedges) $01ff88ab (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default clamp edges (clampedges) $01ff88aa clampneg value (0-15) clamppos value (0-15) rst value 00h read value 00h bits 7-4 clampneg clampneg establishes the trailing edge of the clamp signal relative to the start of each dot period, and is specified in scandotscaler clock periods. bits 3-0 clamppos clamppos establishes the leading edge of the clamp signal relative to the start of each dot period, and is specified in scandotscaler clock periods.
MFC2000 multifunctional peripheral controller 2000 hardware description 7-12 conexant 100723a name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default clk2d control (clk2dctrl) $01ff88c5 select (not used) (not used) shift delay[1] delay[0] invert guardband enable rst. value xxx00000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default clk2d control (clk2dctrl) $01ff88c4 negedge[3:0] posedge[3:0] rst. value x0h read value 00h bit 15 select 0 = selecting sample signal 1 = clk2d bit 12 shift 0 = clk2d synchronous to the rising edge of ihsclk 1 = to the falling edge of ihsclk bit 11-10 delay programmable delay amount 0 = no delay 1 = 1 unit delay 2 = 2 unit delay 3 = 3 unit delay bit 9 invert 0 = normal 1 = invert) bit 8 guardband enable 0 = no guardband 1 = apply guardband bit 7-4 negedge position bit 3-0 posedge position name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default ledctrl[0] edges (led0edges) 01ff88ad negedge[7:0] trailing edge position = (negedge[7:0] * 64) pixels before/after scan start delay rst. value 00h read value 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default ledctrl[0] edges (led0edges) 01ff88ac posedge[7:0] leading edge position = (posedge[7:0] * 64) pixels before/after scan start delay rst. value 00h read value 00h bits 15-8 negedge[7:0] negedge establishes the trailing edge of the envelope for ledctrl signal and is specified in 64 pixel clock periods. bits 7-0 posedge[7:0] posedge establishes the leading edge of the envelope for ledctrl signal and is specified in 64 pixel clock periods.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-13 name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default ledctrl[1] edges (led1edges) 01ff88af negedge[7:0] trailing edge position = (negedge[7:0] * 64) pixels before/after scan start delay rst. value 00h read value 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default ledctrl[1] edges (led1edges) 01ff88ae posedge[7:0] leading edge position = (posedge[7:0] * 64) pixels before/after scan start delay rst. value 00h read value 00h bits 15-8 negedge[7:0] negedge establishes the trailing edge of the envelope for ledctrl signal and is specified in 64 pixel clock periods. bits 7-0 posedge[7:0] posedge establishes the leading edge of the envelope for ledctrl signal and is specified in 64 pixel clock periods. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default ledctrl[2] edges (led2edges) 01ff88b1 negedge[7:0] trailing edge position = (negedge[7:0] * 64) pixels before/after scan start delay rst. value 00h read value 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default ledctrl[2] edges (led2edges) 01ff88b0 posedge[7:0] leading edge position = (posedge[7:0] * 64) pixels before/after scan start delay rst. value 00h read value 00h bits 15-8 negedge[7:0] negedge establishes the trailing edge of the envelope for ledctrl signal and is specified in 64 pixel clock periods. bits 7-0 posedge[7:0] posedge establishes the leading edge of the envelope for ledctrl signal and is specified in 64 pixel clock periods. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default led0 pwm config (led0pwm) $01ff88b3 (not used) (not used) (not used) (not used) (not used) clock divider[2:0] rst. value xxxxx000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default led0 pwm config (led0pwm) $01ff88b2 duty cycle[7:0] rst. value 00h read value 00h
MFC2000 multifunctional peripheral controller 2000 hardware description 7-14 conexant 100723a bits 10-8 clock divider[2:0] the clock used for pwm is scaled according to ?clock divider? setting. bits 7-0 duty cycle[7:0] the period of pwm is divided into 256. the high time of pwm is determined by ?duty cycle?. min frequency (clk_div = 7) ihsclk = 50 ns pwm clk = t(ihsclk ) * (clk_div + 1) = 50 ns * (7 + 1) = 400 ns pwm period = 400 ns * 256 = 102,400 ns = 102.4 us (9.8 khz) max frequency (clk_div = 0) ihsclk = 50 ns pwm clk = ihsclk = 50 ns pwm period = 50 ns * 256 = 12.8 us (78.1 khz) note : in order to have a non-modulated signal, the duty cycle must be set to 0xff. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default led1 pwm config (led1pwm) $01ff88b5 (not used) (not used) (not used) (not used) (not used) clock divider[2:0] rst. value xxxxx000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default led1 pwm config (led1pwm) $01ff88b4 duty cycle[7:0] rst. value 00h read value 00h bits 10-8 clock divider[2:0] the clock used for pwm is scaled according to ?clock divider? setting. bits 7-0 duty cycle[7:0] the period of pwm is divided into 256. the high time of pwm is determined by ?duty cycle?. note : in order to have a non-modulated signal, the duty cycle must be set to 0xff. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default led2 pwm config (led2pwm) $01ff88b7 (not used) (not used) (not used) (not used) (not used) clock divider[2:0] rst. value xxxxx000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default led2 pwm config (led2pwm) $01ff88b6 duty cycle[7:0] rst. value 00h read value 00h
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-15 bits 10-8 clock divider[2:0] the clock used for pwm is scaled according to ?clock divider? setting. bits 7-0 duty cycle[7:0] the period of pwm is divided into 256. the high time of pwm is determined by ?duty cycle?. note : in order to have a non-modulated signal, the duty cycle must be set to 0xff. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default ledctrl config (ledconfig) $01ff88b9 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xx000111b read value 07h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default ledctrl config (ledconfig) $01ff88b8 (not used) (not used) ledctrl[2] sync_select ledctrl[1] sync_select ledctrl[0] sync_select ledctrl[2] position ledctrl[1] position ledctrl[0] position rst. value xx000000b read value 00h bits 5-3 ledctrl[2:0] sync_select 1 = sync is selected, ignoring led pwm config & led edges settings 0 = normal ledctrl when sync_select bit is set and the led is enabled (by setting the corresponding bit in scanctrl register), then the ledctrl will be active from the beginning of scancycle until the end of scancycle. in this mode of operation, the corresponding led pwm & led edges settings are ignored. once the led is disabled, then at the end of scancycle, the ledctrl will not be active anymore. in other words, by setting sync_select bit, the ledctrl is outputing the led enabled which is synchronized with the cyclestart. when sync_select bit is clear and the led is enabled, then the ledctrl operates in normal mode, which depends on the led pwm & led edges settings. bits 2-0 ledctrl[2:0] position 1 = before scanstartdelay 0 = after scanstartdelay this position setting only affects the leading edge of ledctrl envelope. if the place bit is reset, then the ledctrl will be activated after valid pixel. otherwise, if the place bit is set, then ledctrl can be activated right after scancycle. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default scan ia config (scaniaconfig) $01ff88bb adc enable (not used) offsetsel[5] offsetsel[4] offsetsel[3] offsetsel[2] offsetsel[1] offsetsel[0] rst. value xxx00000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default scan ia config (scaniaconfig) $01ff88ba (not used) (not used) gpo on ev_vd[5] gpo on ev_vd[4] gainsel[3] gainsel[2] gainsel[1] gainsel[0] rst. value x0h read value 00h
MFC2000 multifunctional peripheral controller 2000 hardware description 7-16 conexant 100723a in order to apply the content of this register to the analog die, the content must be sent serially by writing to the ?adcserialcmd? register. please refer to the ?adcserialcmd? register description for more information. bit 15 adc enable this bit is used to enable the internal adc. the adc circuit by default is disabled. bit 12-8 offsetsel[4:0] an analog subtracter is used in conjunction with offsetsel in order to remove the dc offset from scanner signal. bit 5 gpo on ev_vd[5] when ?vsc on ev bus? bit, i.e., bit 2 of vscctrl register, is set, then ev_vd[7:0] bus will function as output.. ev_vd[5] output is connected to this bit to function as general purpose output (gpo). bit 4 gpo on ev_vd[4] when ?vsc on ev bus? bit, i.e., bit 2 of vscctrl register, is set, then ev_vd[7:0] bus will function as output.. ev_vd[4] output is connected to this bit to function as general purpose output (gpo). bit 3-0 gainsel[3:0] gainsel is connected to a programmable gain amplifier to adjust the gain of the scanner signal. note : this register is double-buffered. the value written into this register will not be applied to sia immediately. rather, the value will be applied after the start of scancycle. reading this register reflects the value applied to sia. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default adcserialcmd (adcserialcmd) $01ff854f send status (read only) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default adcserialcmd (adcserialcmd) $01ff854e (not used) (not used) (not used) (not used) (reserved) ?0? command type transmit mode[1] transmit mode[0] rst. value xxxx0000b read value 00h bit 15 send status (read only) this bit indicates one of the following statuses: waiting for an event to occur, as selected by ?transmit mode[1:0]?, prior to sending the serial command sending serial command is in progress. the wait for the event can be aborted by clearing ?scanenable? bit on ?scanconfig? register, and the command will not be sent. bit 15 reserved it is important to always write ?0? to this bit. bit 2 command type command type function 0 to send ?offset? and ?gain? settings as stored in ?scaniaconfig? register 1 to send ?adc enable? bit as stored in ?scaniaconfig? register
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-17 bit 1-0 transmit mode[1:0] prior to writing to this register, check the ?send status? bit, and make sure that this bit is clear. if this bit is set, then writing to this register will be ignored. if this bit is clear, then writing to this register will cause the following action based on the ?transmit mode?: transmit mode time to send the serial data 0 right away 1 at the beginning of a scan cycle; no ?scanonce? operation is involved 2 at the end of valid pixel (i.e. the last valid pixel in a line); ?scanonce? operation is involved 3 at the next msint name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default scan control delay (scanctrldelay) $01ff88bd sample delay[1:0] scctrl[6] delay[1:0] scctrl[5] delay[1:0] scctrl[4] delay[1:0] rst. value xx000000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default scan control delay (scanctrldelay) $01ff88bc scctrl[3] delay[1:0] scctrl[2] delay[1:0] scctrl[1] delay[1:0] clamp delay[1:0] rst. value 00h read value 00h bit 15-14 sample delay this setting controls the delay for ?sample? signal. bit 13-12 scctrl[6] delay this setting controls the delay for ?scctrl[6]? signal. bit 11-10 scctrl[5] delay this setting controls the delay for ?scctrl[5]? signal. bit 9-8 scctrl[4] delay this setting controls the delay for ?scctrl[4]? signal. bit 7-6 scctrl[3] delay this setting controls the delay for ?scctrl[3]? signal. bit 5-4 scctrl[2] delay this setting controls the delay for ?scctrl[2]? signal. bit 3-2 scctrl[1] delay this setting controls the delay for ?scctrl[1]? signal. bit 1-0 clamp delay this setting controls the delay for ?clamp? signal. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default adc config (adcconfig) $01ff88bf adclkneg value (0-15) adclkpos value (0-15) rst. value 00h read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default adc config (adcconfig) $01ff88be digital data capture position [3:0] (0-15) data latency[3:0] (0-15) rst. value 00h read value 00h
MFC2000 multifunctional peripheral controller 2000 hardware description 7-18 conexant 100723a bit 15-12 adclkneg (only valid when internal adc is selected) adclkneg establishes the trailing edge of the adclk signal relative to the start of each dot period, and is specified in terms of scandotscaler clock periods. bit 11-8 adclkpos (only valid when internal adc is selected) adclkpos establishes the leading edge of the adclk signal relative to the start of each dot period, and is specified in terms of scandotscaler clock periods. bit 7-4 digital data capture position (valid for external adc only) this setting indicates where the digital data from adc should be captured within a pixel period, and is specified in terms of scandotscaler clock periods. bit 3-0 data latency (valid with either internal or external adc) this setting indicates the latency or pipeline delay as required by adc, and is expressed in the number of pixel clocks. important note on how to program adclk & adsample when an internal adc is selected: 1. the location and the width of adsample must be established first according to the scanner requirement (the analog signal is being sampled while adsample = 1, and at the falling edge of adsample, the signal is stored into an internal capacitor. while adsample = 0, the signal value is being held in the capacitor.) 2. once adsample has been programmed properly, the adclk must be configured according to the following rule: a) adclk must be low while adsample is high
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-19 7.1.3 timing msintcy scanenb current cycle start[0] enb (write to scanctrl reg) start[0] enb_status (read from scanctrl status reg) cycle_start start[0] mode = 1 place = 1 mode = 1 place = 0 mode = 0 place = x mode = 0 mode = 1 0 1 2 3 0 scancycle = 3 write '1' to enablescan bit in scanconfig1 register write '1' to start[0] enable bit in scanctrl register synchonized to cycle_start indicates the beginning of a scan cycle startposedge startnegedge startlength clampdelay scanstartdelay clamplength clampdelay clamplength clampposedge clampnegedge clampposedge clampnegedge clampposedge clampnegedge sampleposedge samplenegedge scanstartdelay scanlength pixels sampleposedge samplenegedge clk2a clk2aposedge clk2anegedge clk1 adsample adsample clamp clamp clamp startoffset figure 7-2. untitled timing diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 7-20 conexant 100723a sccyc_nxt 2 1 3 4 0 2 1 3 4 0 sccyc_ctr sccyc_count sccyc_reset msintirqloc_sync 3 scanirq_set set by hardware clear by firmware (writing to bit 0 of vscirqstatus register) scanirq_cur (assuming scanirqenb = '1') setup.msintirqloc 3 2 2 firmware change the location of msint irq scancycles_sync 4 setup.scancycles 4 3 3 firmware change the number of msint in a scancycle one msint period figure 7-3. untitled timing diagram msintcy scan cycle (counter) f/w writes to scancycle register scan cycle (1 st buffer) 2 3 0 1 2 0 1 3 2 scan cycle (2 nd buffer) 3 2 h/w synchonizes the 1 st and 2 nd buffer at the beginning of a scan cycle cycle_start the beginning of a scan cycle figure 7-4. untitled timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-21 ihsclk clk2a clk1 pixaddr_ctr 100 99 101 dotperiod_ctr 2 0 1 2 0 1 dotscaler_ctr 0 1 0 1 0 1 0 1 0 1 0 1 scan dot scaler =1 50 ns scan dot period = 2 one pixel toggling every pixel clk2apos = 1 clk2aneg = 2 figure 7-5. untitled timing diagram note : the rising and falling edges timing of clk2a also applies to clk2b , clk2c , start , clamp , and adsample .
MFC2000 multifunctional peripheral controller 2000 hardware description 7-22 conexant 100723a cycle_start ledctrl[0]enb ledctrl[0]enb_status ledctrl[0] (write to scanctrl reg) (read from scanctrl status reg) scanstartdelay led0posedge led0negedge led0pwmclkdiv[2:0] led0pwmdutycycle[7:0] write '1' write '0' synchronized to cycle_start ledctrl[1]enb ledctrl[1]enb_status ledctrl[1] (write to scanctrl reg) (read from scanctrl status reg) scanstartdelay led1posedge led1negedge led1pwmclkdiv[2:0] led1pwmdutycycle[7:0] write '1' write '0' synchronized to cycle_start ledctrl[2]enb ledctrl[2]enb_status ledctrl[2] (write to scanctrl reg) (read from scanctrl status reg) scanstartdelay led2posedge led2negedge led2pwmclkdiv[2:0] led2pwmdutycycle[7:0] write '1' write '0' synchronized to cycle_start write scanctrl [13:11] with 100b vsc_irq time write to vsc_irq clear register vsc_irq comes write scanctrl [13:11] with 010b write to vsc_irq clear register vsc_irq comes write scanctrl [13:11] with 001b write to vsc_irq clear register vsc_irq comes (place = 0) (place = 0) (place = 0) [led-time.vsd] figure 7-6. untitled timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-23 0 1 3 0 1 2047 2048 2049 4048 xxxx start scanstartdelay[13:0] (in pixel unit) scanlength[12:0] (number of valid pixels) pixeladr[13:0] ledctrl[0] led0neg[7:0] * 64 led0pos[7:0] * 64 hi- z t = 0 led0pad_en = 0 led0pad_en = 1 (default value from reset) msint 0 sccyccur[4:0] 0 0 2 3 4 0 scancycle[4:0] = 4 (determines the time for scanning a line) led0pos[7:0] * 64 led on-time (no pwm) led0neg[7:0] * 64 figure 7-7. untitled timing diagram notes : 1. msint_period = (msintperiod + 1) * 125 us msintperiod[5:0] is set in msintperiod register (assuming that value in 125usprescaler register has been adjusted to obtain 125 us period) 2. scancycle_period = (scancycle + 1) * msint_period 3. scancycle in conjunction with msintperiod must be selected so that: ihsclk pwmclk pwmpr_ctr pwm 255 0 1 253 254 255 0 clk_div = 1 duty_cycle = 253 * pwmclk_period period = 256 * pwmclk_period programmable fixed programmable figure 7-8. untitled timing diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 7-24 conexant 100723a msintcy current cycle 0 1 2 3 0 3 scan_irq cleared by writing '1' to bit 0 of vscirqstatus register scancycle = 3 3 msint irq loc generated here because msint irq location = 3 & current cycle = 3 figure 7-9. untitled timing diagram the scanner controller will issue adc_start, adc_drdy, and adc_stop as follows: adc_start adc_stop adc_drdy 1 adc_dclk or more 1 adc_dclk wide 1 adc_dclk wide figure 7-10. untitled timing diagram external adc timing summary national: adc 12662 vin s/h data[11:0] min = 5 ns max = 400 ns t conv = 510 - 660 ns pipeline delay (latency) = 1 cycles [adc-national-adc12662.vsd] figure 7-11. untitled timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-25 analog: ad 9220 8 ns data[11:0] data 1 clk vin s1 s2 s3 s4 hold sample min = 100 ns min = 45 ns min = 45 ns pipeline delay (latency) = 3 clk cycles figure 7-12. untitled timing diagram linear: ltc 1412 vin convst data[11:0] min = 20 ns t conv = 240-283 ns pipeline delay (latency) = 1 cycles figure 7-13. untitled timing diagram 7.1.4 firmware operation in order to obtain the optimal digital data, the dynamic range of analog signal must be maximized. in order to maximize the dynamic range of scanner signal, the duration of the light exposure on the sensor must be just right. if it is too short, then the signal will be too low; and if it is too long, then the signal will be saturated. the amount of light exposure can be controlled by having programmable pulse width modulation on the led control. typically, the signal from the sensor has a dc offset. this offset must be removed, and the resulting signal can be amplified to restore the dynamic range. examples of how to setup the registers for various scanners are shown below. these setups are configured for the fastest scanning operation. (only setup, not operation registers are shown) notes : 1.) the value for scan cycle depends on how msint signal is configured. 2.) the led setting may need adjustment according to the proper light intensity for different color.
MFC2000 multifunctional peripheral controller 2000 hardware description 7-26 conexant 100723a manufacturer rohm interface: part # ia3008 ? ze22 scanner description MFC2000 type cis r gnd red led control ledctrl[0] resolution 300 dpi g gnd green led control ledctrl[1] pixels/line 2560 b gnd blue led control ledctrl[2] scan time (color) 9 ms/line si start pulse start[0] scan time (b/w) 1.8~4.5 ms/line clk main clock clk2a data rate 1.5 mhz (max) ao scanner signal vin main clock ?h? duty 25 ? 50 % timing: dotscaler_ctr ihsclk dotperiod_ctr 0 13 0 clk2a start[0] 50 ns start[0] linetime = 3 ms scanin sigtime = 1.792 m s ledctrl[0] can be modulated envelope of analog signal pixel counter 0 2560 2624 4224 pixeltime = 700 ns 1 2 3 4 5 6 7 8 9 10 11 12 13 0 4285 exptime =1.12 ms no delay [rohm?ia3008?ze22.vsd] figure 7-14. untitled timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-27 table 7-1. register setup for rohm?ia3008?ze22 register name bits name value scanconfig scctrl[6:0] invert 0 scctrl[6:2] select xx100b scandotcontrol scan dot scaler[3:0] 0 scan dot period[3:0] 13 startconfig guardbandenb[6:4] 0 guardband[4:0] n/a offset[3:0] 0 length[3:0] 0 startedges startpos[3:0] 0 startneg[3:0] 13 scanstartdelay delay[12:0] 0 clk2aedges clk2apos[3:0] 7 clk2aneg[3:0] 12 clk2bedges clk2bpos[3:0] n/a clk2bneg[3:0] n/a clk2cedges clk2cpos[3:0] n/a clk2cneg[3:0] n/a adcsamplecfg samplepos[3:0] 9 sampleneg[3:0] 11 adcconfig adclkpos[3:0] 0 adclkneg[3:0] 6 dataplace[3:0] 10 datalatency[3:0] clampctrl clampmode n/a clampenb 0 clamplength[6:0] n/a clampdelay clampposition n/a clampdelay[13:0] n/a clampedges clamppos[3:0] n/a clampneg[3:0] n/a ledconfig ledctrl sync_sel[2:0] 0 ledctrl place[2:0] 0 led0edges led0pos[7:0] 41 led0neg[7:0] 66 led1edges led1pos[7:0] 41 led1neg[7:0] 66 led2edges led2pos[7:0] 41 led2neg[7:0] 66 scanlength scanlength[12:0] 2560 scancyles scancycle[4:0] 3 ms
MFC2000 multifunctional peripheral controller 2000 hardware description 7-28 conexant 100723a manufacturer dyna interface: part # dl507?07uah scanner description MFC2000 type cis ledr red led control ledctrl[0] resolution 300 dpi ledg green led control ledctrl[1] pixels/line 2552 ledb blue led control ledctrl[2] scan time (color) 7.5 ms/line si start pulse start[0] scan time (b/w) clk main clock clk2a data rate 2.0 mhz (typ) sig scanner signal vin main clock ?h? duty 25 % (typ) timing: dotscaler_ctr ihsclk dotperiod_ctr 0 9 0 clk2a start[0] 50 ns start[0] linetime = 2.5 ms scanin sigtime = 1.276 m s ledctrl[0] can be modulated envelope of analog signal pixel counter 0 2552 2560 4992 pixeltime = 500 ns 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5000 exptime =1.12 ms delay of 2 pixels figure 7-15. untitled timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-29 table 7-2. register setup for dyna?dl507?07uah register name bits name value scanconfig scctrl[6:0] invert 0 scctrl[6:2] select xx100b scandotcontrol scan dot scaler[3:0] 0 scan dot period[3:0] 9 startconfig guardbandenb[6:4] 0 guardband[4:0] n/a offset[3:0] 0 length[3:0] 0 startedges startpos[3:0] 0 startneg[3:0] 9 scanstartdelay delay[12:0] 0 clk2aedges clk2apos[3:0] 6 clk2aneg[3:0] 8 clk2bedges clk2bpos[3:0] n/a clk2bneg[3:0] n/a clk2cedges clk2cpos[3:0] n/a clk2cneg[3:0] n/a adcsamplecfg samplepos[3:0] sampleneg[3:0] adcconfig adclkpos[3:0] adclkneg[3:0] dataplace[3:0] datalatency[3:0] clampctrl clampmode n/a clampenb 0 clamplength[6:0] n/a clampdelay clampposition n/a clampdelay[13:0] n/a clampedges clamppos[3:0] n/a clampneg[3:0] n/a ledconfig ledctrl sync_sel[2:0] 0 ledctrl place[2:0] 0 led0edges led0pos[7:0] 40 led0neg[7:0] 78 led1edges led1pos[7:0] 40 led1neg[7:0] 78 led2edges led2pos[7:0] 40 led2neg[7:0] 78 scanlength scanlength[12:0] 2552 scancyles scancycle[4:0] 2.5 ms
MFC2000 multifunctional peripheral controller 2000 hardware description 7-30 conexant 100723a manufacturer mitsubishi interface: part # gt3r216 scanner description MFC2000 type cis ledr red led control ledctrl[0] resolution 300 dpi ledg green led control ledctrl[1] pixels/line 2552 ledb blue led control ledctrl[2] scan time (color) 7.5 ms/line si start pulse start[0] scan time (b/w) 1.5 ms/line clk main clock clk2a data rate 3 ? 4 mhz sig scanner signal vin main clock ?h? duty 20 ? 30 % timing: dotscaler_ctr ihsclk dotperiod_ctr 0 4 0 1 2 3 4 0 1 2 3 4 clk2a start[0] 50 ns start[0] linetime = 2.5 ms scanin sigtime = 638 s ledctrl[0] can be modulated envelope of analog signal pixel counter 0 2552 2560 9920 pixeltime = 250 ns delay of 1 pixel figure 7-16. untitled timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-31 table 7-3. register setup for mitsubishi-gt3r216 register name bits name value scanconfig scctrl[6:0] invert 0 scctrl[6:2] select xx100b scandotcontrol scan dot scaler[3:0] 0 scan dot period[3:0] 4 startconfig guardbandenb[6:4] 0 guardband[4:0] n/a offset[3:0] 0 length[3:0] 0 startedges startpos[3:0] 0 startneg[3:0] 4 scanstartdelay delay[12:0] clk2aedges clk2apos[3:0] 4 clk2aneg[3:0] 4 clk2bedges clk2bpos[3:0] n/a clk2bneg[3:0] n/a clk2cedges clk2cpos[3:0] n/a clk2cneg[3:0] n/a adcsamplecfg samplepos[3:0] sampleneg[3:0] adcconfig adclkpos[3:0] adclkneg[3:0] dataplace[3:0] datalatency[3:0] clampctrl clampmode n/a clampenb 0 clamplength[6:0] n/a clampdelay clampposition n/a clampdelay[13:0] n/a clampedges clamppos[3:0] n/a clampneg[3:0] n/a ledconfig ledctrl sync_sel[2:0] 0 ledctrl place[2:0] 0 led0edges led0pos[7:0] 40 led0neg[7:0] 155 led1edges led1pos[7:0] 40 led1neg[7:0] 155 led2edges led2pos[7:0] 40 led2neg[7:0] 155 scanlength scanlength[12:0] 2552 scancyles scancycle[4:0] 2.5 ms
MFC2000 multifunctional peripheral controller 2000 hardware description 7-32 conexant 100723a manufacturer toshiba interface: part # cips218mc300 scanner description MFC2000 type cis pkg w/ ccd ledr red led control ledctrl[0] resolution 300 dpi ledg green led control ledctrl[1] pixels/line 2576 ledb blue led control ledctrl[2] scan time (color) tr start pulse start[0] scan time (b/w) m main clock clk2a data rate 0.1 ? 2.5 mhz rs clock clk2b main clock ?h? duty 50 % rnc clock clk2c timing: dotscaler_ctr ihsclk dotperiod_ctr 0 7 0 clk2a start[0] 50 ns start[0] linetime =2 ms scanin sigtime = 1.0304 m s ledctrl[0] can be modulated envelope of analog signal pixel counter 0 2576 pixeltime = 400 ns 1 2 3 4 5 6 7 0 1 2 3 4 5000 exptime = 1.48 ms 5 6 clk2b clk2c clk2a 50 ns 50 ns 17 dummy pixels 4992 4 clocks (min) figure 7-17. untitled timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-33 table 7-4. register setup for toshiba?cips218mc300 register name bits name value scanconfig scctrl[6:0] invert 0000000b scctrl[6:2] select 11100b scandotcontrol scan dot scaler[3:0] 0 scan dot period[3:0] 7 startconfig guardbandenb[6:4] 0 guardband[4:0] n/a offset[3:0] 1 length[3:0] 4 startedges startpos[3:0] 0 startneg[3:0] 1 scanstartdelay delay[12:0] 16 clk2aedges clk2apos[3:0] 1 clk2aneg[3:0] 4 clk2bedges clk2bpos[3:0] 2 clk2bneg[3:0] 2 clk2cedges clk2cpos[3:0] 3 clk2cneg[3:0] 0 adcsamplecfg samplepos[3:0] sampleneg[3:0] adcconfig adclkpos[3:0] adclkneg[3:0] dataplace[3:0] datalatency[3:0] clampctrl clampmode 1 clampenb 1 clamplength[6:0] 16 clampdelay clampposition 1 clampdelay[13:0] 0 clampedges clamppos[3:0] 7 clampneg[3:0] 7 ledconfig ledctrl sync_sel[2:0] 0 ledctrl place[2:0] 0 led0edges led0pos[7:0] 0 led0neg[7:0] 78 led1edges led1pos[7:0] 0 led1neg[7:0] 78 led2edges led2pos[7:0] 0 led2neg[7:0] 78 scanlength scanlength[12:0] 2576 scancyles scancycle[4:0] 2 ms
MFC2000 multifunctional peripheral controller 2000 hardware description 7-34 conexant 100723a manufacturer nec interface: part # pd3724 scanner description MFC2000 type ccd led control ledctrl[0] resolution 300 dpi tg[3:1] start pulse start[0] pixels 2700 x 3 sel1 color selector1 ledctrl[1] scan time (color) sel2 color selector2 ledctrl[2] scan time (b/w) rb reset clock clk2a data rate 3 mhz (max) 1, 1l shift register clock 1 clk1 main clock ?h? duty 50 % 22l shift register clock 2 clk1 timing: dotscaler_ctr ihsclk dotperiod_ctr 0 6 0 clk1 50 ns start[0] linetime =1.5 ms scanin sigtime = 0.945 ms ledctrl[0] can be modulated envelope of analog signal pixel counter 0 2700 pixeltime = 350 ns 1 2 3 4 5 6 0 1 2 3 4 4285 exptime = 1.48 ms 5 6 inv( clk1 ) clk2a 14 dummy + 49 black + 2 invalid pixels 4224 0 clk1 3150 ns (guardband) 350 ns start[0] 1050 ns (offset) 1050 ns 1050 ns (length) ledctrl[2:1] 2 3 1 figure 7-18. untitled timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-35 table 7-5. register setup for nec ? pd3724 register name bits name value scanconfig scctrl[6:0] invert 0100000b scctrl[6:2] select 00100b scandotcontrol scan dot scaler[3:0] 0 scan dot period[3:0] 6 startconfig guardbandenb[6:4] 7 guardband[4:0] 8 offset[3:0] 2 length[3:0] 2 startedges startpos[3:0] 0 startneg[3:0] 6 scanstartdelay delay[12:0] 65 + 9 = 74 clk2aedges clk2apos[3:0] 4 clk2aneg[3:0] 2 clk2bedges clk2bpos[3:0] n/a clk2bneg[3:0] n/a clk2cedges clk2cpos[3:0] n/a clk2cneg[3:0] n/a adcsamplecfg samplepos[3:0] 0 sampleneg[3:0] 1 adcconfig adclkpos[3:0] adclkneg[3:0] dataplace[3:0] datalatency[3:0] clampctrl clampmode 1 clampenb 1 clamplength[6:0] 49 clampdelay clampposition 1 clampdelay[13:0] 13 + 9 = 22 clampedges clamppos[3:0] 0 clampneg[3:0] 1 ledconfig ledctrl sync_sel[2:0] 6 ledctrl place[2:0] 1 led0edges led0pos[7:0] 0 led0neg[7:0] 66 led1edges led1pos[7:0] n/a led1neg[7:0] n/a led2edges led2pos[7:0] n/a led2neg[7:0] n/a scanlength scanlength[12:0] 2700 scancyles scancyle[4:0] 1.5 ms
MFC2000 multifunctional peripheral controller 2000 hardware description 7-36 conexant 100723a manufacturer nec interface: part # pd3794 scanner description MFC2000 type ccd led control ledctrl[0] resolution 300 dpi tg[3:1] start pulse start[0] pixels 2700 x 3 sel1 color selector1 ledctrl[1] scan time (color) sel2 color selector2 ledctrl[2] scan time (b/w) rb reset clock clk2a data rate 4 mhz (max) 1 shift register clock 1 clk2b main clock ?h? duty 2 shift register clock 2 clk2c timing: dotscaler_ctr ihsclk dotperiod_ctr 0 4 0 50 ns start[0] linetime =1 ms scanin sigtime = 0.675 ms ledctrl[0] can be modulated envelope of analog signal pixel counter 0 2700 1 2 3 4 0 1 2 3 4 3936 exptime = ~1 ms 14 dummy + 48 black + 2 invalid pixels clk1 5000 ns (guardband) 250 ns start[0] 1000 ns (offset) 1000 ns 3000 ns (length) ledctrl[2:1] 2 3 1 0 1 2 3 4 3904 clk2a clk2b pixeltime = 250 ns clk2c figure 7-19. untitled timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-37 table 7-6. register setup for nec ? pd3794 register name bits name value scanconfig scctrl[6:0] invert 0000000b scctrl[6:2] select 11000b scandotcontrol scan dot scaler[3:0] 0 scan dot period[3:0] 4 startconfig guardbandenb[6:4] 6 guardband[4:0] 19 offset[3:0] 3 length[3:0] 11 startedges startpos[3:0] 0 startneg[3:0] 4 scanstartdelay delay[12:0] 83 clk2aedges clk2apos[3:0] 4 clk2aneg[3:0] 1 clk2bedges clk2bpos[3:0] 3 clk2bneg[3:0] 0 clk2cedges clk2cpos[3:0] 4 clk2cneg[3:0] 4 adcsamplecfg samplepos[3:0] 4 sampleneg[3:0] 4 adcconfig adclkpos[3:0] adclkneg[3:0] dataplace[3:0] datalatency[3:0] clampctrl clampmode 1 clampenb 1 clamplength[6:0] 47 clampdelay clampposition 1 clampdelay[13:0] 33 clampedges clamppos[3:0] 2 clampneg[3:0] 2 ledconfig ledctrl sync_sel[2:0] 6 ledctrl place[2:0] 1 led0edges led0pos[7:0] 0 led0neg[7:0] 60 led1edges led1pos[7:0] n/a led1neg[7:0] n/a led2edges led2pos[7:0] n/a led2neg[7:0] n/a scanlength scanlength[12:0] 2700 scancyles scancycle[4:0] 0
MFC2000 multifunctional peripheral controller 2000 hardware description 7-38 conexant 100723a manufacturer sony interface: part # ilx516k scanner description MFC2000 type ccd led control ledctrl[0] resolution 400 dpi rog (3) start pulse start[0] pixels 3648 x 3 sel1 color selector1 ledctrl[1] scan time (color) sel2 color selector2 ledctrl[2] scan time (b/w) rs reset clock clk2a data rate 5 mhz (max) 1, lh shift register clock 1 clk2b main clock ?h? duty 50 % 2 shift register clock 2 clk2c timing: dotscaler_ctr ihsclk dotperiod_ctr 0 3 0 clk2a 50 ns start[0] linetime =1.5 ms scanin sigtime = 0.7296 m s ledctrl[0] can be modulated envelope of analog signal pixel counter 0 3648 pixeltime = 200 ns (min) 1 2 3 7500 exptime = 1.4976 ms clk2b clk2c 63 dummy pixels 7488 clk2b 800 ns (min) 200 ns start[0] 200 ns (min = 50 ns) 800 ns (min) ledctrl[2:1] 1 0 2 0 1 2 3 0 1 2 3 0 1 2 min = 45 ns min = 45 ns valid output typ = 10 ns typ = 10 ns figure 7-20. untitled timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-39 table 7-7. register setup for sony ? ilx516k register name bits name value scanconfig scctrl[6:0] invert 0110000b scctrl[6:2] select 11100b scandotcontrol scan dot scaler[3:0] 0 scan dot period[3:0] 3 startconfig guardband[6:4] 7 guardband[4:0] 9 offset[3:0] 0 length[3:0] 3 startedges startpos[3:0] 1 startneg[3:0] 3 scanstartdelay delay[12:0] 63 + 10 = 73 clk2aedges clk2apos[3:0] 1 clk2aneg[3:0] 3 clk2bedges clk2bpos[3:0] 2 clk2bneg[3:0] 3 clk2cedges clk2cpos[3:0] 2 clk2cneg[3:0] 3 adcsamplecfg samplepos[3:0] 3 sampleneg[3:0] 3 adcconfig adclkpos[3:0] adclkneg[3:0] dataplace[3:0] datalatency[3:0] clampctrl clampmode 1 clampenb 1 clamplength[6:0] 49 clampdelay clampposition 1 clampdelay[13:0] 10 + 14 = 24 clampedges clamppos[3:0] 1 clampneg[3:0] 1 ledconfig ledctrl sync_sel[2:0] 6 ledctrl place[2:0] 1 led0edges led0pos[7:0] 0 led0neg[7:0] 117 led1edges led1pos[7:0] n/a led1neg[7:0] n/a led2edges led2pos[7:0] n/a led2neg[7:0] n/a scanlength scanlength[12:0] 3648 scancyles scancyle[4:0] 1.5 ms
MFC2000 multifunctional peripheral controller 2000 hardware description 7-40 conexant 100723a external circuit required for sony?ilx516k interface: sony - ilx516k vout r vout g vout b +12 v 100 ? 5.1k ? +12 v 100 ? 5.1k ? +12 v 100 ? 5.1k ? MFC2000 scanin ledctrl[2] ledctrl[1] analog inverter analog mux figure 7-21. external circuit required for sony?ilx516k interface led timing for sony?ilx516k start[0] ledctrl[0] ledctrl[2:1] select red select green select blue expsoure time as required by red sensor expsoure time as required by green sensor expsoure time as required by blue sensor used as selectors for analog mux figure 7-22. led timing for sony?ilx516k
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-41 7.2 serial programming interface the serial programming interface is a two-wire bidirectional serial bus, which provides a simple and efficient way for data exchange between devices. main features: ? only two bus lines are required; a serial interface data (sid) and a serial interface clock (sic) ? master?transmitter & master?receiver ? schmitt trigger on sid input ? synchronization capability (allowing slave to add wait state by pulling the clock low) ? optional interrupt or polling operation ? optional firmware operation for manual control of the spi bus ? soft reset 7.2.1 function description physical connection mfc2k (master) slave sid_n out sic in sid in sic_n out sid_n out sic in sid in sid (serial interface data) sic (serial interface clock) sic_n out pm[0]/gpo[0]/ spi_sid /eadc_d[9]/t_ext_breq pm[1]/gpo[1]/ spi_sic /eadc_d[8]/t_ext_back figure 7-23. serial programming interface, physical connection notes : 1. master is the device that initiates a transaction, generates clock signal, and terminates the transaction. 2. data and clock can only be driven low, and cannot be driven high. the pull-up resistors are responsible to create a logic 1 . this configuration forms wire ? and connection. 3. slave can only drive the clock signal to add wait state. 4. there is no minimum requirement for clock frequency.
MFC2000 multifunctional peripheral controller 2000 hardware description 7-42 conexant 100723a bus protocol start slave address r/w ack data ack data ack stop 7-bit 1-bit 8-bit 8-bit data transfer (n bytes + acknowledge) figure 7-24. bus protocol sid sic b7 b6 b1 b0 b7 b6 b1 b0 a/a start slave address r/w a n x (8-bit data) n x (a/a) stop [spi_timing.vsd] figure 7-25. serial programming interface, timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-43 start condition sid sic data is pulled low while clock is still high, followed by pulling the clock low. clock and data will be held low. stop condition sid sic clock is released to high, followed by releasing data to high. bit transfer sid sic address/data bit must be valid while sic is high. getting ack sid sic lsb master slave wire 'z' 'z' lsb 'h' '0' '0' 'h' 'z' wac end of write this is the condition after master transmitted data to slave, which will be referred as wac (write acknowlege). slave is giving acknowledge by driving the data line low. master is getting the acknowledge by generating a clock pulse to capture the acknowledge. giving ack sid sic master slave wire lsb '0' 'h' lsb 'z' 'z' '0' 'z' rac end of read 'h' this is the condition after master received data from slave, which will be referred as rac (read acknowledge). master is giving acknowledge to the slave by driving data line low and by generating a clock pulse. slave is receiving the acknowledge from master.
MFC2000 multifunctional peripheral controller 2000 hardware description 7-44 conexant 100723a clock stretching slave can add wait state as needed by stretching the low period of the clock. this will slow down the bus as shown below. master's sic slave's sic sic wait state figure 7-26. stretching the low period of the clock 7.2.2 register description name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default spi control (spictrl) $01ff854b (not used) (not used) (not used) (not used) (not used) (not used) (not used) wri (read only) rst. value xxxxxxx0b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default spi control (spictrl) $01ff854a rst rea sta sto rac wac sid sic rst. value 00h read value 00h bit 8 wri ? writing this is a read only bit which indicates the writing operation. reading a 1 means the spi is in the process of sending/writing data to slave. bit 7 rst ? reset writing a 1 to this bit will cause the spi logic controller to be resetted. if spi is in operation while rst bit is set, then the operation will be terminated. reading a 1 from this bit indicates that rst operation is active. after the reset, both sid and sic lines will be released. bit 6 rea ? read writing a 1 to this bit will generate 8 clocks to read data from slave, and spi will capture serial data into the upper byte of ?spi_data? register. reading a 1 from this bit indicates that rea operation is active. bit 5 sta ? start writing a 1 to this bit will generate start condition. reading a 1 from this bit indicates sta operation is active. bit 4 sto ? stop writing a 1 to this bit will generate stop condition. reading a 1 from this bit indicates sto operation is active. bit 3 rac ? read acknowledge writing a 1 to this bit will generate acknowledge condition after read operation in which the master will: 1. generate clock pulse 2. drive sid low reading a 1 from this bit indicates rac operation is active.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-45 bit 2 wac ? write acknowledge writing a 1 to this bit will generate acknowledge condition after write operation in which the master will: 1. generate clock pulse 2. not drive sid but will capture acknowledge bit from slave and store it into bit 8 of ?spi_stat? register reading a 1 from this bit indicates wac operation is active. bit 1 sid ? serial input data this bit is used to control the sid line directly, and it is only valid if the ?manual operation? bit in spi_config is equal to 1. when sid = 1, then spi is not driving the sid line. when sid = 0, then spi will drive sid line low. bit 0 sic ? serial input clock this bit is used to control the sic line directly, and it is only valid if the ?manual operation? bit in spi_config is equal to 1. when sic = 1, then spi is not driving the sic line. when sic = 0, then spi will drive sic line low. note : in normal case, only one of bit [7:2] should be set. however, if for some reasons, more than one bits are set, then the hardware will respond according to the following priority. other bit(s) that are set will be ignored. priority operation 1rst 2sto 3sta 4rea 5rac 6wac 7wri
MFC2000 multifunctional peripheral controller 2000 hardware description 7-46 conexant 100723a name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default spi status (spistat) $01ff854d (not used) (not used) (not used) (not used) (not used) (not used) (not used) received ack (read only) rst. value xxxxxxx0b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default spi status (spistat) $01ff854c (not used) (not used) (not used) (not used) (not used) (not used) sid line (read only) sic line (read only) rst. value xxxxxx00b read value 00h bit 8 received ack this is a read only bit which is only valid after writing a 1 to ?wac? bit and after verifying that wac operation is completed, i.e., wac bit is 0. after master sends data to slave, master must check if slave has received the data properly. this checking is done by requesting acknowledge from slave. in this situation, master is sending a clock pulse, and capture the acknowledge on sid line while sic is high. this is the acknowledge stored in bit 8. bit 1 sid ? serial input data line this is a read only bit which comes directly from the sid pin. bit 0 sic ? serial input clock line this is a read only bit which comes directly from the sic pin. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default spi configuration (spiconfig) $01ff88c1 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default spi configuration (spiconfig) $01ff88c0 manual operation (not used) (not used) (not used) spi interrupt enable clock mode clk divider[1] clk divider[0] rst. value 0xxx0000b read value 00h bit 7 manual operation by setting this bit, firmware can control the sid and sic directly by writing to bit 1 and bit 0 of spi_ctrl register. bit 3 spi interrupt enable by setting this bit, the interrupt from spi is enabled. at the end of rea, sta, sto, rac, wac, or wri operation, the interrupt will be active in order to indicate the completion of operation. once the firmware has serviced this interrupt, it can be cleared by writing a 1 to bit 1 of ?vscirqstatus? register. bit 2 clock mode bit 1-0 clock divider[1:0]
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-47 clock mode = 0 clock mode = 1 div[1:0] sic freq div[1:0] sic freq 0 1.2 khz 0 104 khz 1 9.8 khz 1 156 khz 2 39 khz 2 208 khz 3 78 khz 3 312 khz note : the freqencies specified above are based on iclk = 10mhz. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default spi data (spidata) $01ff88c3 read data[7] (read only) read data[6] (read only) read data[5] (read only) read data[4] (read only) read data[3] (read only) read data[2] (read only) read data[1] (read only) read data[0] (read only) rst. value 00h read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default spi data (spidata) $01ff88c2 write data[7] write data[6] write data[5] write data[4] write data[3] write data[2] write data[1] write data[0] rst. value 00h read value 00h bit 15-8 read data[15:8] the data received is stored in this location. bit 7-0 write data[7:0] the data transmitted comes from this location. writing to spidata register will initiate the transmission of bit[7:0]. it should be noted that if the writing occurs while act = 1, then the current transmission will be corrupted.
MFC2000 multifunctional peripheral controller 2000 hardware description 7-48 conexant 100723a 7.2.3 firmware operation initialization: select the desired frequency for sic by writing the appropriate value to ?spi_config? register transmission: start write to 'spi_data' reg write 0x0020 to 'spi_ctrl' reg send the 7-bit slave address + "w" bit send more data? no yes write 0x0010 to 'spi_ctrl' reg generate stop condition end no generate start condition write to 'spi_data' reg receive & clear spi_irq write 0x0004 to 'spi_ctrl' reg generate wac condition receive & clear spi_irq receive & clear spi_irq [spi_fw_tx.vsd] figure 7-27. firmware operation ? ? ? ? transmission
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-49 reception: start write to 'spi_data' reg write 0x0020 to 'spi_ctrl' reg send the 7-bit slave address + "r" bit expect more data? no write 0x0010 to 'spi_ctrl' reg generate stop condition; end no generate start condition receive & clear spi irq write 0x0004 to 'spi_ctrl' reg generate wac condition write 0x0040 to 'spi_ctrl' reg initiate read operation of sending clock pulses & capturing serial data read 'spi_data' reg yes write 0x0080 to 'spi_ctrl' reg generate rac condition receive & clear spi irq receive & clear spi irq receive & clear spi irq [spi_fw_rx.vsd] figure 7-28. firmware operation ? ? ? ? reception
MFC2000 multifunctional peripheral controller 2000 hardware description 7-50 conexant 100723a 7.3 video controller main features: ? capture a frame from an external video decoder device ? support itu?r bt.656 or vesa video interface port (vip) format of ycrcb 4:2:2 ? store captured frame into memory in a non-interlace format ? software interrupt at the end of a frame capture itu?r bt.656 ? data format: c b , y, c r , y, etc yy c b c r ? control structure: ff, 00, 00, xy xy contains the video timing reference code xy = {1, f, v, h, p3, p2, p1, p0}, where f = field v = vertical h = horizontal (0 = sav, 1 = eav) p3, p2, p1, p0 = error protection bits, with p3 = v xor h, p2 = f xor h, p1= f xor v, p0 = f xor v xor h xy f v h type 80 0 0 0 sav 9d 0 0 1 eav ab 0 1 0 sav b6 0 1 1 eav c7 1 0 0 sav da 1 0 1 eav ec 1 1 0 sav f1 1 1 1 eav ? control insertion: 1. at the beginning of a line: sav (start of active video) 2. at the end of a line: eav (end of active video) ? number of pixels per line is 720. ? the following control codes are inserted for every valid line: field start line end line 0 ff, 00, 00, 80 ff, 00, 00, 9d 1 ff, 00, 00, c7 ff, 00, 00, da
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-51 vesa vip ? dummy byte/ invalid pixel code: 00 (between sav and eav) ? number of pixels per line is not restricted to 720 ? the most significant bit of xy byte is called task bit (t-bit), which can be 1 or 0. convention ? f = 0 (field = 1) is an odd field ? f = 1 (field = 2) is an even field ? odd field is the top field ? even field is the bottom field 7.3.1 function description pins connection to external video capture device: video capture MFC2000 data[7:0] clk ev_vd[7:0] /eadc_d[11:4] ev_clk figure 7-29. connection to external video capture device 7.3.2 register description name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default video capture control (vidcapturectrl) $01ff8549 (not used) (not used) (not used) (not used) (not used) (not used) (not used) video error (read only) rst. value xxxxxxx0b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default video capture control (vidcapturectrl) $01ff8548 (not used) (not used) (not used) (not used) (not used) (not used) (not used) start capture rst. value xxxxxxx0b read value 00h bit 8 video error this status bit indicates that error has been detected in capturing the video signal. the error is detected based on the line length comparison between the specified number of bytes per line (i.e., the value in videolinecfg register) to the actual number of bytes captured. if any line within a frame does not match videolinecfg register, this bit will be set. at the beginning of the next video capture, this error bit will be cleared. bit 0 start capture by setting this bit, the hardware will start the process of capturing a frame of video data. once a complete frame has been captured, the hardware will clear this bit. the status of capturing process can be known by reading this bit. reading a 1 indicates that the hardware is busy.
MFC2000 multifunctional peripheral controller 2000 hardware description 7-52 conexant 100723a name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default video line config (vidlinecfg) $01ff88c7 (not used) (not used) (not used) (not used) (not used) linesize[10] linesize[9] linesize[8] rst. value xxxxx000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default video line config (vidlinecfg) $01ff88c6 linesize[7] linesize[6] linesize[5] linesize[4] linesize[3] linesize[2] linesize[1] 0 rst. value 00h read value 00h bit 10-1 linesize[10:1] this register defines the maximum number of bytes to be captured per line. the value in this register must be written prior to initiating the video capture. bit 0 is a constant zero in order to ensure that line size is an even number, i.e., on the word boundary. if the number of actual data is more than this value, then the actual data will be truncated. it should be noted that at the end of every line, one or two byte of zeros will be added in order to indicate the end of line, and at the same time the additional zeros will guarantee that the line length is on the word boundary. whenever the actual data does not match the linesize, the ?video error? bit in ?video capture config? register will be set to 1. note : the jump or skip parameter in dma setting must be at least 1 halfword bigger than the ?linesizecfg? in order to take into account the additional zeros at the end of line. example of line too short vidlinecfg = 10 bytes number of actual data from video decoder = 9 bytes number of actual data stored into memory = 9 bytes number of zeros inserted into memory = 1 byte final line size = 10 bytes example of line too long vidlinecfg = 10 bytes number of actual data from video decoder = 11 bytes number of actual data stored into memory = 10 bytes number of zeros inserted into memory = 2 byte final line size = 12 bytes example of line is just right vidlinecfg = 10 bytes number of actual data from video decoder = 10 bytes number of actual data stored into memory = 10 bytes number of zeros inserted into memory = 2 byte final line size = 12 bytes
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-53 name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default video line length status (vidllstat) $01ff88c9 (not used) (not used) (not used) (not used) (not used) vidll[10] (read only) vidll[9] (read only) vidll[8] (read only) rst. value xxxxx000b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default video line length status (vidllstat) $01ff88c8 vidll[7] (read only) vidll[6] (read only) vidll[5] (read only) vidll[4] (read only) vidll[3] (read only) vidll[2] (read only) vidll[1] (read only) vidll[0] (read only) rst. value 00h read value 00h bit 10-0 vidll[10:0] this register indicates the number of bytes per line and not the number of pixels per line. the value in this register is updated continuously at the end of every line. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default video odd field length status (vidoddflstat) $01ff88cb (not used) (not used) (not used) (not used) (not used) (not used) (not used) vidoddfl [8] (read only) rst. value xxxxxxx0b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default video odd field length status (vidoddflstat) $01ff88ca vidoddfl [7] (read only) vidoddfl [6] (read only) vidoddfl [5] (read only) vidoddfl [4] (read only) vidoddfl [3] (read only) vidoddfl [2] (read only) vidoddfl [1] (read only) vidoddfl [0] (read only) rst. value 00h read value 00h bit 8-0 vidoddfl [8:0] this register indicates the number of lines in odd field. the value in this register is updated continuously at the end of every odd field. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default video even field length status (videvenflstat) $01ff88cd (not used) (not used) (not used) (not used) (not used) (not used) (not used) videvenfl [8] (read only) rst. value xxxxxxx0b read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default video even field length status (videvenflstat) $01ff88cc videvenfl [7] (read only) videvenfl [6] (read only) videvenfl [5] (read only) videvenfl [4] (read only) videvenfl [3] (read only) videvenfl [2] (read only) videvenfl [1] (read only) videvenfl [0] (read only) rst. value 00h read value 00h bit 8-0 videvenfl [8:0] this register indicates the number of lines in even field. the value in this register is updated continuously at the end of every even field.
MFC2000 multifunctional peripheral controller 2000 hardware description 7-54 conexant 100723a 7.3.3 timing data is sampled at the rising edge. the control codes indicate the beginning and the end of a valid line, with invalid pixels inserted. ff 00 00 80 c b y c r y data clk one line field = 0 ff 00 00 9d 00 valid c b y start of line for field = 0 end of line for field = 0 ff 00 00 c7 c b y c r y data clk one line field = 1 ff 00 00 da 00 valid c b y start of line for field = 1 end of line for field = 1 figure 7-30. untitled timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 7-55 7.3.4 firmware operation firmware sequence of operations: 1. setup the external video capture device via two-wire serial interface 2. poll the status register in external video capture device via two-wire serial interface 3. read vidllstat and vidoddflstat registers if video signal is detected 4. setup dma based on the values stored in vidllstat and vidoddflstat registers 5. write to vidlinesizecfg register based on the vidllstat 6. start the video capture by writing to vidcapturectrl register dma operation: odd field address even field address step/jump 0 n+1 n+2 1 2 n start stop signal from video decoder device, indicating the end of the odd field signal from video decoder device, indicating the end of frame capture figure 7-31. dma operation dma features: ? clear internal counter after address/other registers are written ? selection bit (scan/video) ? scan: 1 address will be used, and operation is simple ? video: 2 addresses will be used, and operation is complex as shown above
MFC2000 multifunctional peripheral controller 2000 hardware description 7-56 conexant 100723a this page is intentionally blank.
multifunctional peripheral controller 2000 MFC2000 100723a conexant 8-1 8. adc 8.1 padc and scan analog front end 8.1.1 general description clamp offset adjustment sample gain[3:0] adc adcrefp adcrefn adcvc adclk adcout[11:0] scin adva adgd advd clamp offset[5:0] sample gain[3:0] adclk adcout[11:0] reference adcvc adcrefp adcrefn tadcref tadcref adcrefp adcrefn adcvc pga offset[5:0] + + _ dac -0.1 v 1.9 v ext interface (pad & pin) int interface symbols: signal names: lowercase : digital uppercase: analog 0 v 3 v adga figure 8-1. untitled figure
MFC2000 multifunctional peripheral controller 2000 hardware description 8-2 conexant 100723a table 8-1. untitled table name description adclk clock for adc circuit the maximum frequency of this clock is 5 mhz. this clock is guaranteed to be low while ?sample? is high. clamp clock for clamping circuit the maximum frequency of this clock is 5 mhz. gain[3:0] selector for gain adjustment on pga circuit offset[5:0] selector for offset adjustment on dac circuit sample clock for sampling circuit the maximum frequency of this clock is 5 mhz. the minimum (high) pulse width is 50 ns. adcout[11:0] digital data from adc circuit tadcref analog signal as a reference voltage for tadc table 8-2. untitled table name description adcrefn an internally generated reference voltage adcrefp an internally generated reference voltage adga ground return from analog circuits adgd ground return from digital circuits adva +3.3v power supply for analog circuits advc an internally generated reference voltage advd +3.3v power supply for digital circuits scin analog input for scanner signal 8.1.2 offset adjustment this offset adjustment contains dac which takes digital input to configure the dac and analog subtraction to subtract the incoming scanner signal with the analog signal from the dac. this adjustment is used to remove/reduce the dark level offset on the scanner signal. the adjustment on dac value is described below: table 8-3. offset adjustment on dac parameter min typ max units offset[5:0] 000000 -0.1 v 11111 1.9 v
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 8-3 8.1.3 programmable gain amplifier (pga) table 8-4. programmable gain amplifier (pga) parameter min typ max units input voltage range (gain = 1) 0 3 v gain[3:0] (in hex) 0 -1.25 -1 -0.75 db 1 -0.25 0 0.25 db 2 0.75 1 1.25 db 3 1.75 2 2.25 db 4 2.75 3 3.25 db 5 3.75 4 4.25 db 6 4.75 5 5.25 db 7 5.75 6 6.25 db 8 6.75 7 7.25 db 9 7.75 8 8.25 db a 8.75 9 9.25 db b 9.75 10 10.25 db c 10.75 11 11.25 db d 11.75 12 12.25 db e 12.75 13 13.25 db f 13.75 14 14.25 db note: scanner output will be sampled at the falling edge of the ?sample? signal
MFC2000 multifunctional peripheral controller 2000 hardware description 8-4 conexant 100723a 8.1.4 pipelined analog-to-digital converter (padc) table 8-5. pipelined adc (padc) parameter min typ max units resolution 12 bits speed 5msps accuracy differential nonlinearity (dnl) -1 0.5 +1 lsb integral nonlinearity (inl) -2 1 +2 lsb power supply rejection 1 mv/v output format $ binary unsigned latency 16 adclk 8.1.5 timing diagram scin (scanner output) sample adclk adcout[11:0] a pixel period programmable sample position within pixel period (min width = 50 ns) s1 d2 d1 s2 latency guarantees to be low while sample is high table 8-6. padc timing diagram 8.1.6 adcvrefp, adcvrefn, and adcvc the adcvrefp and adcvrefn voltages provide positive and negative references for adcs while vc is used as common mode voltage in the design of adc and pga. these voltages are decoupled with external capacitors (0.1 f) to reduce thermal noise and also to provide high frequency ac current for sampling. 8.1.7 tadcref parameter min typ max units tadcref 2.370 2.390 2.410 v
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 8-5 8.2 tadc 8.2.1 function description thermal adc provides the analog to digital functionality for low speed analog signals. a simplified block diagram of tadc is shown below. - + 6-bit dac +/- 1/2 bit 9-bit up/down counter 6 msbs ad[5:0] senin[0],[1],[2], or tadcref [tadc-simple.vsd] table 8-7. tadc block diagram the tadc includes a 6-bit dac, a comparator and a 9-bit self tracking up/down counter. the up/down counter is incremented or decremented based on the polarity of the comparator output. the most significant 6 bits of the counter are used to generate the dac reference signal to the comparator. the comparator compares this reference voltage to the external analog input signals, senin[2:0], or tadcref. after settling, the counter value (and thus the dac digital value) represents the a-to-d conversion of the input signal. the least significant bits of the counter are used to average out the comparator fluctuations which occurs at the settling point. the counter is set to a mid-point value on the power-on reset so that it settles more quickly. the frequency of updating the counter is programmable. the tadc can be operated in two modes. by default, the manual mode will be selected. in this mode, the firmware will select the analog input. then, the firmware must wait for at least for 256 * tadcclk period to allow the tadc to settle prior to reading the data. in the automatic mode, the hardware will do the selection for each analog input in rotation. each analog input will be selected periodically, and the data from each channel will be stored in different register at the same rate as channel selection.
MFC2000 multifunctional peripheral controller 2000 hardware description 8-6 conexant 100723a 8.2.2 register description name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default tadc control (tadcctrl) $01ff8001 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default tadc control (tadcctrl) $01ff8000 (not used) tadcclk select[1] tadcclk select[0] update select[1] update select[0] channel select[1] channel select[0] mode rst. value x0000000b read value 00h bit 6-5 tadcclk select[1:0] the frequency for tadc counter is programmable according to the following table. tadcclk select[1:0] tadcclk frequency tadcclk frequency (assuming iclk = 10mhz) 0 freq(iclk)/64 156 khz 1 freq(iclk)/16 625 khz 2 freq(iclk)/8 1.25 mhz 3 freq(iclk)/4 2.5 mhz bit 4-3 update select[1:0] in the auto mode, the frequency of updating each register is determined by the setting on these bits. update select[1:0] update frequency update frequency (with tadcclk = 156 khz) update frequency (with tadcclk = 5 mhz) 0 freq(tadcclk)/2048 76 hz 2.4 khz 1 freq(tadcclk)/1024 152 hz 4.8 khz 2 freq(tadcclk)/512 304 hz 9.8 khz 3 freq(tadcclk)/256 609 hz 19.5 khz bit 2-1 channel select [1:0] this channel selection is only valid for manual mode (i.e., mode = 0). channel select[1:0] selected channel 0 senin[0] 1 senin[1] 2 senin[2] 3 tadcref bit 0 mode when mode = 0, then the manual mode is selected. in this manual mode, the channel selected must be done by the firmware, by setting the desired channel selection in bit 2 & bit1. when mode = 1, then the automatic mode is selected. in this auto mode, the selection for the analog mux will be performed automatically by the hardware, and the data on three registers corresponding to each channel will be updated accordingly.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 8-7 note : in automatic mode, only channel 0, 1, and 2 will be automatically selected. thus, in order to obtain the value for tadcref, manual mode must be used, and ?channel select? must be set to 3. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default tadc instant data (tadcinsdata) $01ff8003 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default tadc instant data (tadcinsdata) $01ff8002 (not used) (not used) data[5] (read only) data[4] (read only) data[3] (read only) data[2] (read only) data[1] (read only) data[0] (read only) rst. value xx000000b read value 00h bit 5-0 data the data in this register comes directly from tadc. thus, it gives the instant value from tadc regardless of the tadc operation mode. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default tadc ch 0 data (tadcch0data) $01ff8005 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default tadc ch 0 data (tadcch0data) $01ff8004 (not used) (not used) data[5] (read only) data[4] (read only) data[3] (read only) data[2] (read only) data[1] (read only) data[0] (read only) rst. value xx000000b read value 00h bit 5-0 data this data is only valid when the auto mode is selected. name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default tadc ch 1 data (tadcch1data) $01ff8007 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default tadc ch 1 data (tadcch1data) $01ff8006 (not used) (not used) data[5] (read only) data[4] (read only) data[3] (read only) data[2] (read only) data[1] (read only) data[0] (read only) rst. value xx000000b read value 00h bit 5-0 data this data is only valid when the auto mode is selected.
MFC2000 multifunctional peripheral controller 2000 hardware description 8-8 conexant 100723a name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default tadc ch 2 data (tadcch2data) $01ff8009 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default tadc ch 2 data (tadcch2data) $01ff8008 (not used) (not used) data[5] (read only) data[4] (read only) data[3] (read only) data[2] (read only) data[1] (read only) data[0] (read only) rst. value xx000000b read value 00h bit 5-0 data this data is only valid when the auto mode is selected. 8.2.3 firmware operation general setup: 1. select the desired tadclk frequency 2. select the desired mode of operation in manual mode: 3 mm . select the right channel (?tadcctrl[2:1]?) 4 mm . wait for at least ?tadclk? period * 256 for tadc output to be stable 5 mm . read tadc data from ?tadcinsdata? register. (then, go to step 3 mm to select other channel) in automatic mode: 3 am . select the desired update frequency (?tadcctrl[4:3]?) 4 am . wait for at least tadc update period * 3 (only need to wait once after the above step. this wait guarantees each channel has been selected and its value has been stored in the corresponding register) 5 am . read tadc data from ?tadcch1data?, ?tadcch2data?, ?tadcch3data? at any time for latest data.
multifunctional peripheral controller 2000 MFC2000 100723a conexant 9-1 9. bi-level resolution conversion 9.1 functional description the bi-level resolution conversion logic in the MFC2000 performs expansion (converting from lower to higher resolution) and reduction (converting from higher to lower resolution) of horizontal image data. vertical line oring can also be performed for image reduction in the vertical direction. there are two data sources that can be selected for this bi-level resolution conversion block. one is t4/t6 decompressor and another is the external memory. the data from the t4/t6 decompressor is serially input to this bi-level resolution conversion logic. the data from the external memory is input to this bi-level resolution conversion logic through the dma operation. the dma operation for the data from the external memory uses the dma channel 9. if the t4/t6 decompressor is selected as the data source, the dma channel 9 request is blocked. the data from this resolution conversion logic is output to the external memory also through the dma operation. the dma operation for the output data uses the dma channel 8 (see figure 9-1). the mfc2k adds the following features to the brc block: 1. a first and last black data detector to indicate the first and last halfword out of the brc that contains printable data. 2. the ability the change the oring algorithm for hoizontal reduction. because the bi-level resolution conversion is a slave logic, the dma channel 9 for inputting data from memory has the block size control function. once the block size limit is reached during the dma operation. the dma controller gives a signal to the bi-level resolution conversion logic that indicates the end of process. then, the bi- level resolution conversion logic will deactivate the dma request, disable the fifo, and start the flush operation. after the flush operation the bi-level resolution conversion interrupt will be generated to the interrupt controller. before cpu gets out of the interrupt routine, cpu needs to write the new block size into the dma9blocksize register of the dma controller (even the same block size) to clear the interrupt. then, cpu needs to write a 1 and then, immediately write a 0 to bit 1 of the biresconvctrl register to tell hardware to convert a new line (reset the resolution conversion logic). if the data from the t4/t6 decompressor is serially input to this bi-level resolution conversion logic, this bi-level resolution conversion logic is treated as a part of t.4/t6 logic. the t.4 line length (instead of block size of dma channel 9) and t.4 interrupt (instead of the bi-level resolution conversion interrupt) are used. furthermore,, this bi- level resolution conversion logic is enabled by setting bit 5 in the ?t4config? register in the t4/t6 compression/decompression logic. the flush operation depends on the fifo direction. if the fifo is being read by the local side and written by the system side, a flush will simply reset all of the internal fifo pointers, thereby removing the data. if the fifo is being written by the local side and read by the system side, a flush will cause a dma request to be generated. in addition, if there is a single byte in the holding register, it will be treated as a halfword (the contents of the msbyte of the halfword are indeterminate). because of this, it is important for firmware to first check for the presence of a single byte in the holding register (via the byte present bit in the fifo control register). each fifo is composed of 4 halfwords, a holding register, and a control register. firmware can randomly access all the fifo registers under the following restrictions: ? when the fifo is enabled - reads may return invalid data, writes are blocked ? when the fifo is disabled - read/write operations are properly performed ? random access of the fifo registers is useful in saving and restoring the state of the fifo. this should only be done when the fifo is disabled.
MFC2000 multifunctional peripheral controller 2000 hardware description 9-2 conexant 100723a 9.1.1 horizontal conversion conversion in the horizontal direction is performed in this logic block by adding or removing a programmable number of pixels at the position which decided by the bi-level resolution conversion algorithm. pixels are added based on a programmable 7-bit base-3 counter and the expansion mode bits (2 bits). input pixel number needs to be a multiple of 16. the output pixel number of this block is also a multiple of 16. table 9-1. untitled table the expected expansion ratio the expansion mode the programmed expansion ratio the expansion result 100% x < 200% 0x x 200% x < 300% 1 x - 100% x 300% x < 400% 2 x - 200% x pixels are removed based on the same programmable 7-bit base-3 counter used for the expansion. data can be reduced down to 0.0457% (1/2187 x) and expanded up to 399.95% (~4x). to preserve image quality, it is recommended that an input line be reduced by no more than 2/3 times (66.67%) it's original resolution (this will ensure that 2 consecutive input pixels will never be removed). the following block diagram depicts the brc block diagram. the functions are broken up into the blocks that represent the imdividule vhdl that make up the brc design. note that the two blocks, vertical oring and brc out fifo, outputs are tied together. this represents the fact that only one of these output modes are operational at time. brc in fifo parallel to serial in mux brc counters filter, oring oring algo. shingle horizontal shifter serial to parallel vertical oring brc out fifo resolution converter dma data in dma data out dma req 8 dma req 9 t4 serial data in figure 9-1: bi-level resolution conversion block diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 9-3 9.1.2 vertical conversion expansion in the vertical direction is accomplished by the processor duplicating lines as needed to achieve the desired expansion ratio. reduction in the vertical direction is accomplished by the processor either deleting lines or oring lines together as needed to achieve the vertical reduction ratio. oring of lines is also done by the resolution conversion logic. when oring is enabled, each byte of the current line's line buffer data is ored with the corresponding byte from the previous line. the dma channel associated with the resolution conversion block performs a read-modify (or) -write operation. the dma read and write accesses do not occur on consecutive bus cycles. the firmware should set the dma channel start address for the line to be ored equal to the address for the previous line. the threshold of the oring function is selectable. if the threshold value is 0, all the black pixels in the current line will be used for the oring function. in order to reduce the background image noise, the threshold value can be set from 1 to 7. if the threshold value is set to 2, the single black pixels and 2 contiguous black pixels in the current line will not be used for the oring function. 9.1.3 shingling shingling is a process in which color intensity was built up in the course of several passes of the head for the inkjet printing. the objective is to print a portion of the data on each of the passes, using a checkerboard mask to decide which pixels to print on each pass and which pixels to mask out. this allows time for dots of ink printed on one pass to dry somewhat before adjacent ink dots are printed on subsequent passes, thereby improving quality. the checkerboard varies with the level of shingling in use. this level is described as a percentage, with 50, 33, and 25 percent shingling levels having been discussed to date. briefly: 50 percent shingling requires two passes of the head. the matrix below shows a section of the pixels on the page, with the number being the pass of the head on which the pixel in printed: 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 33 percent shingling requires three passes to build up full intensity: 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 25 percent shingling requires four passes: 1 3 2 4 1 3 2 4 1 3 2 4 1 3 2 4 1 3 2 4 1 3 2 4 2 4 1 3 2 4 1 3 2 4 1 3 2 4 1 3 2 4 1 3 2 4 1 3 1 3 2 4 1 3 2 4 1 3 2 4 1 3 2 4 1 3 2 4 1 3 2 4 2 4 1 3 2 4 1 3 2 4 1 3 2 4 1 3 2 4 1 3 2 4 1 3 paper moves a portion of the height of the nozzle array between passes of the head, so different nozzles print different dots on a scanline. in this situation, the data for the scanline must be moved from the band buffers to the print buffers several times, with a mask applied along the way so that only part of the data gets through on each move. note that printing is slower when shingling is in use, so bandwidth is not significantly affected. also note that the mask changes between scanlines.
MFC2000 multifunctional peripheral controller 2000 hardware description 9-4 conexant 100723a 9.1.4 horizontal shift function assume that the color inkjet head is used. there are 3 color groups. there are 16 nozzles for each color group on the inkjet head. the image data is usually line-based. for the inkjet printing, we can?t feed the line based data right into the inkjet head. the line-based image data needs to be rearranged to match the inkjet head firing order and will be no longer line-based. as you can see from the diagram at the next page, if nozzle 1 in the top nozzle group needs the 1st pixel of line 1, nozzle 2 in the top nozzle group needs the (np)th pixel of line 2. if there is a total of 48 nozzles, we will need to group 3 halfwords (48 pixels) of data from different lines, different columns, and different color planes. then, another 3 half-word group for the next firing cycle. these 3 half-word groups will be sent to the external print asic. the external print asic will map these 48 pixels to the right nozzle location and control the fire sequence and timing within one firing cycle. in order to do inkjet printing, the line-based printing data from different color planes for each printing swath need to be prepared by firmware. under the assumption above, 48 lines (16 lines/color group) of data need to be prepared for one printing swath by firmware. the vertical pitch (vp) in the diagram below is taken care of by the firmware and the dma operation. then, bi-level resolution conversion block fetches the line-based printing data through dma operation. the line- based printing data is serially processed in the bi-level resolution conversion block. the process order is bi-level resolution conversion -> singling -> horizontal shift -> oring (optional). after these processes, the shifted line- based print data will be put back to the printing buffer by the dma operation. the nozzle pitch (np) and horizontal pitch (hp) in the diagram below are taken care of by the horizontal shifter in the bi-level resolution conversion block. for example, the np is 8 pixels and hp is 18 pixels. we want to prepare the shifted line-based printing data for nozzle 1 of the top group in the diagram below, the horizontal shifter will insert (8+18) zeros in the beginning of this line. if we want to prepare the shifted line-based printing data for nozzle 2 of the top group in the diagram below, the horizontal shifter will insert 18 zeros in the beginning of this line. if we want to prepare the shifted line-based printing data for nozzle 1 of the middle group in the diagram below, the horizontal shifter will insert 8 zeros in the beginning of this line. if we want to prepare the shifted line-based printing data for nozzle 2 of the middle group in the diagram below, the horizontal shifter will insert nothing in the beginning of this line. the actual shifting amount for each line needs to be changed according to the inkjet head which you are using and the mechanical orientation. all the pixels needed for one firing cycle will be at the same column after the horizontal shift process. the number of zeros inserted in the beginning of lines is programmable from 0 to 63. if extra zeros (>63 ) are needed, multiple of 16 zeros need to be prepared into memory by firmware. finally, the bit rotation block gets the shifted line-based printing data through the dma operation. the bit rotation block groups 48 pixels at different lines and at the same column to 3-halfword data for one firing cycle (see the bit rotation section for details).
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 9-5 np hp vp 1 2 3 4 5 7 6 8 ng-3 ng-1 ng-2 ng 2 lines 1 line np - nozzle pitch in pels vp - vertical pitch between nozzle groups in pels hp - horizontal pitch between nozzle groups in pels. ng - number of nozzles in nozzle group. note: odd nozzle columns are located on the left in this figure. figure 9-2. the physical nozzle diagram for typical inkjet heads the boundary condition also needs to be considered. the line length (pixels/line) of the bi-level resolution conversion input and output data is a multiple of 16 (see the bi-level resolution conversion section for details). if we insert different number of zeros in the beginning of lines, all the lines will end at different columns (not end at the same halfword boundary). therefore, control bits need to be used. it indicates the total number of halfwords of zeros that needs to be added either at the beginning and at the end of each line (see the diagram below). 0 - 4 halfwords can be set in the register. 324 halfwords / line example: 26 zeros 324 halfwords / line line1 line2 18 zeros 6 zeros 14 zeros 324 halfwords / line 8 zeros 324 halfwords / line line17 line18 24 zeros 32 zeros 324 halfwords / line 26 zeros 324 halfwords / line line33 line34 18 zeros 6 zeros 14 zeros the register for the total zeros (halfwords) = 2, set for all lines the register for zeros in front (pixels) =26, 18, 8, or 0, set for each line figure 9-3. untitled figure
MFC2000 multifunctional peripheral controller 2000 hardware description 9-6 conexant 100723a 9.1.5 first and last black data detector design below is a schematic representation of the black data detector. the counter and registers get cleared at the start of each line. on the left side of the diagram is the half word counter that is incremented each time a half word is pushed into the fifo (lcl_nxt). when the line starts, each time a lcl_nxt or lcl_wr shifts data into the output fifo holding register, the serial data is checked for black data. if black data is detected, the end of white flag is set. once set, the logic waits until the counter is incremented, (the holding register is pushed into the fifo data register). then the new count value is loaded into the first black data register. as data continues to be shifted into the fifo, the logic at the bottom of the figure 1-2-2 continues to check for black data. each time black data is detected the blk data det flag is set. after that half word is loaded into the fifo data register (counter counts), the counter value is loaded into the last black data register. 9.2 register description external memory setup ? the external memory is selected as the data source by setting bit 2 in the biresconvctrl register to one in the bi-level resolution conversion block. ? the block size of the data in the external memory for the bi-level resolution conversion is set in the dma9blocksize register of the dma controller. ? vertical line oring for the resolution converted data is enabled by setting bit 0 in the biresconvctrl register in the bi-level resolution conversion block. ? the bi-level resolution conversion is initiated by setting bit 1 (first to 1 and then, to 0) in the biresconvctrl register in the bi-level resolution conversion block. t4/t6 control ? t4/t6 decoder bi-level resolution conversion is enabled by setting bit 5 in the ?t4config? register in the t4/t6 compression/decompression logic. ? vertical line oring for the t4 decoded data is enabled by setting bit 3 in the ?t4control? register in the t4/t6 compression/decompression logic. vertical oring for t4 decoded data is only valid if resolution conversion is also enabled. programming the expansion/reduction ratio the bi-level resolution conversion ratio register (biresconratio) controls the horizontal resolution conversion expansion or reduction ratio. the biresconratio register is cleared on reset. the value programmed into the register is the number of pixels to add or remove per 2187 pixels (expressed as a 7 digit base-3 number).
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 9-7 input data fifo control register for the data from the external memory (for dma channel 9): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: bi-level resolution conversion input data fifo control (bircinfifoctrl) $01ff807b fifo enabled (r) data request (r) fifo ready (r) fifo dma threshold fifo output pointer rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: bi-level resolution conversion input data fifo control (bircinfifoctrl) $01ff807a (not used) holding register full (not used) fifo data quantity fifo input pointer rst value x0x00000b read value 00h bit 15 this bit indicates that the fifo is active and capable of generating dma requests. bit 14 this bit is essentially a copy of the dma request output signal and indicates that the fifo wishes to transfer data. bit 13 this bit indicates that the fifo can accept data transfers to/from the local logic. this bit is low when the data direction is into the local logic and the fifo is empty or when the data direction is out of the local logic and the fifo is full. bit 12-10 this bit field indicates at which point the fifo should issue a dma request. it is compared with the fifo data quantity bit field to determine when this should occur. legal values are from 0 to 4. values greater than 4 are treated as 4. bit 9-8 this bit field indicates which byte of the fifo quad halfword structure is the next to be used as output data. bit 6 this bit indicates that there is a full word in the holding register bit 4-2 this bit field indicates the number of quad halfwords that contain data. valid values are from 0 to 4. bit 1-0 this bit field indicates which byte of the fifo quad halfword structure is the next to receive input data. note : it is strongly recommended that the fifo be disabled before firmware writes to the fifo control register. the fifo control register contains data that is essential to the fifo?s operation. if this data is changed while the fifo is operating, unpredictable operation will result.
MFC2000 multifunctional peripheral controller 2000 hardware description 9-8 conexant 100723a input data holding register for the data from the external memory (for dma channel 9): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: bi-level resolution conversion input data holding register (bircinhold) $01ff8079 data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: bi-level resolution conversion input data holding register (bircinhold) $01ff8078 data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value 00h read value 00h input data fifo halfword[3:0] for the data from the external memory (for dma channel 9): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: bi-level resolution conversion input data fifo (bircinfifox) data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: bi-level resolution conversion input data fifo (bircinfifox) data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value 00h read value 00h address assignment for input fifo halfword[3:0] the input fifo halfword the register name address input fifo halfword 3 bircinfifo3 01ff8077-76 input fifo halfword 2 bircinfifo2 01ff8075-74 input fifo halfword 1 bircinfifo1 01ff8073-72 input fifo halfword 0 bircinfifo0 01ff8071-70 output data fifo control register for the data to the external memory (for dma channel 8): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: bi-level resolution conversion output data fifo control (bircoutfifoctrl) $01ff808b fifo enabled (r) data request (r) fifo ready (r) fifo dma threshold fifo output pointer rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: bi-level resolution conversion output data fifo control (bircoutfifoctrl) $01ff808a (not used) holding register full (not used) fifo data quantity fifo input pointer rst value x0x00000b read value 00h
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 9-9 bit 15 this bit indicates that the fifo is active and capable of generating dma requests. bit 14 this bit is essentially a copy of the dma request output signal and indicates that the fifo wishes to transfer data. bit 13 this bit indicates that the fifo can accept data transfers to/from the local logic. this bit is low when the data direction is into the local logic and the fifo is empty or when the data direction is out of the local logic and the fifo is full. bit 12-10 this bit field indicates at which point the fifo should issue a dma request. it is compared with the fifo data quantity bit field to determine when this should occur. legal values are from 0 to 4. values greater than 4 are treated as 4. bit 9-8 this bit field indicates which byte of the fifo quad halfword structure is the next to be used as output data. bit 6 this bit indicates that there is a full word in the holding register bit 4-2 this bit field indicates the number of quad halfwords that contain data. valid values are from 0 to 4. bit 1-0 this bit field indicates which byte of the fifo quad halfword structure is the next to receive input data. note : it is strongly recommended that the fifo be disabled before firmware writes to the fifo control register. the fifo control register contains data that is essential to the fifo?s operation. if this data is changed while the fifo is operating, unpredictable operation will result. output data holding register for the data to the external memory (for dma channel 8): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: bi-level resolution conversion output data holding register (bircouthold) $01ff8089 data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: bi-level resolution conversion output data holding register (bircouthold) $01ff8088 data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value 00h read value 00h
MFC2000 multifunctional peripheral controller 2000 hardware description 9-10 conexant 100723a output data fifo halfword[3:0] for the data to the external memory (for dma channel 8): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: bi-level resolution conversion output data fifo (bircoutfifox) data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: bi-level resolution conversion output data fifo (bircoutfifox) data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value 00h read value 00h address assignment for output fifo halfword[3:0] the output fifo halfword the register name address output fifo halfword 3 bircoutfifo3 01ff8087-86 output fifo halfword 2 bircoutfifo2 01ff8085-84 output fifo halfword 1 bircoutfifo1 01ff8083-82 output fifo halfword 0 bircoutfifo0 01ff8081-80 bi-level resolution converter ratio registers: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: bi-level resolution conversion ratio (biresconratio) 00ff807d add/delete 729 or 1458 pixels per 2187 input pixels 0:= 0 pixels 1:= not allowed 2:= 729 pixels 3:= 1458 pixels add/delete 243 or 486 pixels per 2187 input pixels 0:= 0 pixels 1:= not allowed 2:= 243 pixels 3:= 486 pixels add/delete 81 or 162 pixels per 2187 input pixels 0:= 0 pixels 1:= not allowed 2:= 81 pixels 3:= 162 pixels add/delete 27 or 54 pixels per 2187 input pixels 0:= 0 pixels 1:= not allowed 2:= 27 pixels 3:= 54pixels rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: bi-level resolution conversion ratio control (biresconratio) 01ff807c add/delete 9 or 18 pixels per 2187 input pixels 0:= 0 pixels 1:= not allowed 2:= 9 pixels 3:= 18 pixels add/delete 3 or 6 pixels per 2187 input pixels 0:= 0 pixels 1:= not allowed 2:= 3 pixels 3:= 6 pixels add/delete 1or 2 pixels per 2187 input pixels 0:= 0 pixels 1:= not allowed 2:= 1pixels 3:= 2 pixels expansion/r eduction mode 0=exp. 1=red. simple or enable rst value 00h read value 00000000 b bit 15-2 sets ratio for reduction/expansion of image data bit 1 sets expansion or reduction mode bit 0 turns on simple oring mode of 2 pixels for horizontal reduction
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 9-11 bi-level resolution conversion control register: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: bi-level res. conversion control (biresconctrl) 01ff807f (not used) (not used) (not used) (not used) (not used) (not used) (not used) flush fifo (w) flush status (r) rst value xxxxxxx0b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: bi-level res. conversion control (biresconctrl) 01ff807e expansion mode 0 = 100% x < 200% 1 = 200% x < 300% 2 = 300% x < 400% oring threshold setting 0= no threshold 1-7= threshold value 1-7 data source selection 0=t4/t6 1=ext. mem. new line write 1 and then, 0 " convert a new line enable or of orig. line buffer with current scan line rst value 00h read value 00h bit 8 for write, 1 " flush fifo. for read, 1 " flush needed. bit 7-6 these two bits sets the resolution conversion hardware?s expansion range. if the value of these two bits is ?n? and the expected expansion ratio is x, the ratio ?x-(n* 100%)? needs to be set into the biresconratio register. bit 5-3 n = the threshold value for the oring function, n = 0-7. it means that oring is done to (n+1) contiguous 1?s only when bit 0 is set to 1. bit 2 data source selection when this bit is set to 0, data is serially from the t4/t6 decompressor. when this bit is set to 1, data is from the external memory through the dma operation (dma channel 9). bit 1 convert a new line resolution conversion logic is reset. firmware needs to write a 1 and then, immediately write a 0 to tell hardware to convert a new line. bit 0 enable or of orig. line buffer with current scan line (scanorenb) (this bit is only used when the external scan device is selected as the data source of the resolution conversion). 1 = enable bi-level vertical or'ing of the scanner line buffer data. this bit can be used to accomplish normal mode or'ing and vertical reduction. note : if you don?t want to do image expansion or image reduction, the resolution conversion ratio is 100%. you need to program bits[7:6] of the biresconctrl register to ?00b? and program the biresconratio register to ?0000h?.
MFC2000 multifunctional peripheral controller 2000 hardware description 9-12 conexant 100723a shingling mask register: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: shingling mask register (shinglingmask) $01ff808d (not used) (not used) (not used) (not used) mask bit 11 mask bit 10 mask bit 9 mask bit 8 rst value xxxx1111h read value 0fh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: shingling mask register (shinglingmask) $01ff808c mask bit 7 mask bit 6 mask bit 5 mask bit 4 mask bit 3 mask bit 2 mask bit 1 mask bit 0 rst value ffh read value ffh this is a loadable circular right-shift register which firmware can load a mask. a 1 in a mask bit means to let that pixel pass through and a 0 in a mask bit means to block that pixel and output 0 for that pixel. the output of this shift register (lsb) gates with the serial data from the resolution convertor on each bi-level resolution conversion clock. the shift register is clocked in sync with the serial to parallel converter so that the mask rotates in sync with the serial data. this 12-bit shingling mask register supports 50, 33, and 25 percent shingling. for example, for the 33 percent shingling, firmware should load 001001001001, 010010010010, or 100100100100, depending on the scanline and pass in question. the number of zeros inserted in a line for the horizontal shifter: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: the number of zeros in a line (hszerono) $01ff808f (not used) (not used) (not used) (not used) (not used) data bit 2 data bit 1 data bit 0 rst value xxxxx000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: the number of zeros in a line (hszerono) $01ff808e (not used) (not used) data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value xx000000b read value 00h bit 10-8 the total number of zeros (halfwords) in a line 0 = nothing is added 1 = 1 halfword (16 zeros) 2 = 2 halfwords (32 zeros) 3 = 3 halfwords (48 zeros) 4 = 4 halfwords (64 zeros) 5-7 = not used bit 5-0 the number of zeros (pixels) in the beginning of a line, from 0 to 63 zeros note : if value 5, 6, or 7 is put into this register, 4 halfword (64 zeros) will be used.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 9-13 first black data: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: the first black data location count (firstblkdatcnt) $01ff806d (not used) (not used) (not used) (not used) data bit 11 data bit 10 data bit 9 data bit 8 rst value xxxx0000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: the first black data location count (firstblkdatcnt) $01ff806c data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value 00000000b read value 00h bit 11-0 the first black data location gives the half word count that black data first appeared in output of the brc. if the first half word contains black data the register will remain at 000h. if the second half word contains data the register will contain 0001h etc. if black data in not present in the entire line (all white line), register will be equal to the line length. first half word location = register value + 1. note : starting a new line will reset the counter last black data: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: the last black data location count (lastblkdatcnt) $01ff806f (not used) (not used) (not used) (not used) data bit 11 data bit 10 data bit 9 data bit 8 rst value xxxx0000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: the last black data location count (lastblkdatcnt) $01ff806e data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value 00000000b read value 00h bit 11-0 the last black data location gives the half word count that black data last appeared in output of the brc. if black data in not present in the entire line (all white line), register will read 000h. if only the first half word contains black data the register will read 001h. if the second half word contains data the register will contain 0002h etc. if the last half word contains black data the register will be equal to the total number of half words out of the brc for that line. last half word location = register value. note : starting a new line will reset the counter
MFC2000 multifunctional peripheral controller 2000 hardware description 9-14 conexant 100723a total colored pixel counter: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: total colored pixels printer (totalblkdatcntr) $01ff806b (not used) (not used) data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value xxxx0000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: total colored pixels printer (totalblkdatcntr) $01ff806a data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value 00000000b read value 00h bit 13-0 total colored pixel counter reading this register will return the total number of colored pixels printed since the last time the register was cleared. writing to this register will clear it.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 9-15 9.3 resolution conversion programming examples figure 9-4 is a flowchart that shows the procedure for determining the resolution conversion register values for both expansion and reduction modes: expand or reduce ? expand reduce notes: 1) input = input resolution (number of pixels/input line) 2) output = output resolution (number of pixels/output line) 3) for expansion, output < (4*input) 4) for reduction, output < input 5 ) for best results in reduction , ( in p ut-out p ut ) /in p ut <= 1/3 compute pixels to add per 2187 input pixels: int{[(output-(m+1)*input)/input] * 2187 + 2/3} m: expansion mode compute pixels to remove per 2187 input pixels: int{[(output-input)/input] * 2187} represent pixels to add as a sum of numbers: (3**n) and ( 2 * (3**n) ) where n=0, 1, ... 6 represent pixels to remove as a sum of numbers: (3**n) and (2 * (3**n)) where n = 0, 1, ...6 fill in both registers according to sum and register definition fill in both registers according to sum and register definition figure 9-4: resolution conversion programming the number of pixels to add in expansion mode is determined from the integer portion of: pixels to add per 2187 input pixels = {[ (output pixels per line - (m+1) * input pixels per line)/input pixels per line ] * 2187 +2/3} m: the expansion mode note: 2/3 is added in this equation in order to guarantee that the truncated result will be greater than or equal to the desired number of output pixels per line. the number of pixels to remove in reduction mode is determined from the integer portion of: pixels to remove per 2187 input pixels = {[(input pixels per line - output pixels per line)/input pixels per line] * 2187} note: for best results, the number of pixels removed (per 2187 pixels) in reduction mode should be less than or equal to 729. {i.e., [(input pixels - output pixels)/input pixels] < = 1/3}
MFC2000 multifunctional peripheral controller 2000 hardware description 9-16 conexant 100723a the number of pixels to add or remove per 2187 pixels is next converted to a 7 digit base-3 number. each digit in the base-3 number is weighted as: msd lsd digit n0123456 weight 1/3 1/9 1/27 1/81 1/243 1/729 1/2187 note : msd = most significant digit, lsd = lease significant digit. each digit can take on 3 possible values: 0, 1, or 2; corresponding to adding or removing (0, 1 or 2) * 3 (6-n) pixels for every 3 7 input pixels or, equivalently, adding or removing 0,1, or 2 pixels for every 3 (n+1) pixels. note: the actual number of pixels output from the resolution conversion block will always be a multiple of 16 pixels. example: reduction of 2048 pixel/line to 1728 pixel/line (b4 to a4 reduction) given: input resolution = 2048 pixel/line output resolution = 1728 pixel/line notes: 1. output resolution must be a multiple of 16. 2. (input resolution - output resolution)/input resolution < = 1/3 for best results (i.e., consecutive pixels will not be removed)) in this case, (input resolution - output resolution)/input resolution = 320/2048 = 5/32. therefore, ideally 5 pixels will be removed for every 32 input pixels. compute the number of pixels to remove per 2187 input pixels: int{ [(input-output)/input]*(2187) } = int{ [(2048-1728)/2048]*(3**7) } = int { [320/2048]*2187 } = int { 341.71875 } = 341 therefore, 341 pixels will be removed for every 2187 input pixels. represent the number of pixels to add per 2187 input pixels using powers of 3: using figure 9-1 determine which combination of powers of 3 digits are required to represent 341. the table should be filled from top to bottom. the sum of the enabled digits should equal 341 as illustrated below: 341 = 243 + 81 + 9 + 6 + 2 therefore, digits 243, 81, 9, 6, and 2 should be enabled in the table.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 9-17 table 9-2: procedure to determine pixels to remove pixels to remove per 2187 input pixels yes/no 1458 n 729 n 486 n 243 y 162 n 81 y 54 n 27 n 18 n 9y 6n 2y 1n table 9-3 lists common resolution conversion values. table 9-3: resolution conversion examples conversion dots/inch input dots/line output dots/line ideal # of pixels/line to insert (remove) pixels to insert (remove) per 2187 resconmsd (hex value) resconlsd (hex value) 200 to 300 1728 2456 728 922 $8e $28 200 to 300 1728 2400 672 851 $8a $ac 200 to 360 1728 2952 1224 1549 $c8 $88 200 to 600 1728 3280 1552 1964 $f0 $cc 200 to 720 1728 3280 1552 1964 $f0 $cc 200 to 300 2048 2456 408 436 $2e $28 200 to 360 2048 2952 924 966 $8f $e0 200 to 600 2048 3280 1232 1316 $b8 $cc 200 to 720 2048 3280 1232 1316 $b8 $cc 200 to 200 2048 1728 (320) (341) $28 $be
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multifunctional peripheral controller 2000 MFC2000 100723a conexant 10-1 10. external print asic interface the interface signals used between the MFC2000 and the external print asic are described in this section. they are basically the external arm system bus interface signals. conexant?s alcore chip is an external print asic and it has the p1284 master port to talk to the p1284 slave port in the printer. 10.1 interface between the MFC2000 and external print asic the MFC2000 asic is the master that controls the system bus and all other control signals. the MFC2000 firmware configures and controls the external print asic by setting registers in the external print asic through the system bus. see figure 10-1. auxclk can be used as the clock base for the external print asic. no matter auxclk or external osc is used for the external print asic, the external print asic needs to resynchronize all the signals and accesses for the metastable problems caused by different clocks. the MFC2000 internally uses siuclk and iclk which are different from the external print asic. the interrupt prtirqn is used to tell the MFC2000 that further settings or actions are needed for the external print asic. the register bits in the external print asic may be used to indicate which settings or actions need to be performed. if the extra interrupt channel is required, the external irq13n and irq11 can be also used for the external print asic. these three interrupt input signals are resynchronized twice for the metastable issues. the external print asic needs to be designed with the compatible cpu read/write bus timing and dma bus timing used in the MFC2000 asic. the external dma channel between the MFC2000 asic and the external print asic is dma channel 2. the external print asic may get the print data from the bit rotation block if the bit rotation block is used or get the print data from the external memory if the bit rotation is done by host or the external print asic. 1. the external print asic gets the print data from the external memory. when the external print asic generates the dma request (dmareq2) to request the printing data, the MFC2000 will respond with the dma acknowledge (dmaack2) at the valid access cycle. at the same cycle, the MFC2000 will generate the read strobe, address, and the external chip select signals to read one byte or halfword of print data out of the external memory and put on the data bus. at the rising edge of the read strobe when dmaack2 is high (dmaack acts as a chip select), the external print asic latches this one byte or halfword printing data in. if additional data bytes or halfwords are required by the external asic, it may leave the dmareq2 active. if no additional data is required, the asic should pull the dmareq2 inactive immediately after dmaack goes low. dma address will be incremented, decremented, or jumped during the dma operation according to the fetch order of the print data in the external memory (see the dma controller section). note : no matter the data bus is byte or halfword wide, the memory data bus size must match with the data bus size of the external print asic. the endian control bit for the dma2 needs to be 0. the endian mode can?t be changed during the dma operation. 2. the external print asic gets the print data from the bit rotation block. when the external print asic generates the dma request (dmareq2) to request the printing data, the MFC2000 will respond with the dma acknowledge (dmaack2) at the valid access cycle after the print data ready in the output register of the bit rotation block. at the same cycle, the MFC2000 will generate the read strobe, address, and internal chip select signals to read one halfword of print data out of the output register of the bit rotation block and put on the data bus. the MFC2000?s siu may generate two access cycles for the byte-wide external data bus (the bit 8 of the dma2config register needs to be set to 0) or one access cycle for the halfword-wide external data bus (the bit 8 of the dma2config register needs to be set to 1). at the rising edge of the each read strobe when dmaack2 is high (dmaack acts as a chip select), the external print asic latches this one byte or halfword printing data in. if additional data bytes or halfwords are required by the external asic, it may leave the dmareq2 active. if no additional data is required, the asic should pull the dmareq2 inactive immediately after dmaack goes low. the dma address is fixed during the dma operation (see the dma controller section and the bit rotation section).
MFC2000 multifunctional peripheral controller 2000 hardware description 10-2 conexant 100723a ? cs4n, cs3n, or cs2n may be used as the chip select signal for accessing registers in the external print asic (see memory map section) amfpc print asic auxclk prtirqn dmareq2 dmaack2 system data bus system address bus cs figure 10-1. print asic interface 10.1.1 examples 10.1.2 motor control examples of the inkjet print head module vertical movement the vertical motor stepping control logic in the MFC2000 may be used for the inkjet printing (see section 12.1). for laser printing, this internal vertical motor stepping control logic is not used. horizontal movement the horizontal stepper motor control logic or the horizontal dc motor control logic should be in the external print asic. whenever the external print asic needs the new timer value(s) or the pwm value(s) which is used to control the time interval between steps or the dc motor speed, the external print asic generates the interrupt (prtirqn) to the MFC2000 asic. then, the MFC2000 cpu will write the new timer value(s) to the register(s) in the external print asic in the interrupt subroutine.
multifunctional peripheral controller 2000 MFC2000 100723a conexant 11-1 11. bit rotation logic 11.1 functional description bit rotation logic is responsible for preparing line-based image data to be used for a color or mono inkjet head. it is designed to be completely universal, so that any inkjet head may be supported regardless of nozzle configuration, provided there is only one nozzle per line of the printed image. an example of a typical 3-color inkjet head is shown. np hp vp 1 2 3 4 5 7 6 8 ng-3 ng-1 ng-2 ng 2 lines 1 line np - nozzle pitch in pels vp - vertical pitch between nozzle groups in pels hp - horizontal pitch between nozzle groups in pels. ng - number of nozzles in nozzle group. color1 color2 color3 figure 11-1. nozzle diagram of a typical programmable inkjet head the inkjet head shown is only an example. there are many other configurations that may be supported. the bi- level resolution conversion block works in conjunction with firmware to ensure that all parameters that correspond to nozzle shifts are removed before the image data is deposited in the swath buffer for removal by the bit rotation block. in addition, the bit rotation block does not need to distinguish the difference between mono or inkjet color modes. a few examples of nozzle configurations that can be supported are shown in the figures. these are only to show examples of the universal design.
MFC2000 multifunctional peripheral controller 2000 hardware description 11-2 conexant 100723a nozzle example a nozzle example b line 1 line 3 line 2 etc... figure 11-2. examples of nozzle head configurations because the firmware and bi-level resolution conversion block work in conjunction to remove all nozzle shift parameters, the bit rotation block may always view the data in such a way that it views the nozzles as always being one column of n nozzles, where n corresponds to the number of nozzles on the inkjet head itself. in fact, the only configuration information that the bit rotation block needs to know is the number of nozzles on the inkjet head, the shuttle direction, the width of the line being printed, and the warp. the figure shows how the bit rotation block views the swath regardless of the actual physical nozzle configuration. line 1 line 3 line 2 line n n = number of nozzles in inkjet head figure 11-3. nozzle configuration by bit rotation block (regardless of physical nozzle configuration) the brb works in conjunction with 2 dma channels of the dma controller. within the MFC2000, the dma channels used are channels 2 and 3. channel 3 is used to ?fetch? data from the external swath buffer that resides in the system?s image memory, and is referred to as the swath fetcher dma channel from here on. dma channel 2 is used to transfer ?packed? or rotated image data to the external print asic, and will be referred to as the bit packer dma channel from here on. the brb uses a local memory (in the brb block) to perform its rotation operation. words are ?fetched into the local memory, and then bits are picked out of the halfword and then ?packed? or shifted into an output register, in effect, rotating the swath image data by 90 degrees. the internal buffer size within the bit rotation block is 512 x 1 halfword (16 bits). this buffer is further subdivided into two separate 256 x 16 bit ?banks? for reasons of system performance. while one 256 x 16-bit buffer is being operated upon, the other 256x16-bit buffer may be filled by the fetcher dma channel. because of this, the system only needs to keep up with the print rate, which in the worst case scenario, is 256 bits every fire cycle if 256 nozzles are used.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 11-3 once the data is prepared for output by the bit rotation block, it may be retrieved by the external print asic via the bit packer dma channel. the brb issues the ready signal to indicate that a halfword of data is ready for retrieval to the dma controller. then, the dma controller will grant the dma channel 2 access cycle by activating the dmaack2 when system bus is available if dmareq2 is active and brb output ready signal is active. 11.2 block diagram a high-level block diagram of the bit rotation block is shown. note that the internal ram is double-banked, so that these operations of fetching and packing can occur simultaneously (however, they are not allowed to occur to/from the same bank at the same time). brb_regs ? this block is used to hold the internal registers of the brb. the registers are split into setup registers, operation registers, and test registers. each group has a separate chip select sent by the siu. brb_memif ? this block has three separate interfaces: the siu, the swath fetcher, and the bit packer. if a bit rotation operation is in progress (rotatestart = 1 in the rotctrl register), siu local memory access is locked out, and only the swath fetcher and bit packer blocks may access the memory at this time. if the rotatestart bit is not set, then the siu has access to the 1 kb memory through locations 01ff9000h-01ff93ffh. swath fetcher ? this block works in conjunction with channel 3 of the dma controller to transfer image data from the swath buffer to the local sram for bit rotation. bit packer ? this block is responsible for the actual rotation of image data. it performs this rotation by picking bits out the local sram and constructing the final rotated output data for the external print asic. brbsync ? the brb_regs and swath fetcher blocks operate at the siuclk frequencies, while the bit packer and the brb_memif blocks operate at ihsclk frequencies. the purpose of this block is to synchronize communications between the internal blocks of the brb. swath fetcher brbsync control, status , and data registers bit packer 512 x 16 local sram brb control and register rd/wr signals data mux brb local sram memory controller ipb_di[15:0] ipb_do[15:0] brb local memory access control signals siuclk ihsclk resn brb block dma control and handshaking signals figure 11-4. MFC2000 bit rotation block diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 11-4 conexant 100723a 11.2.1 swath fetcher the swath fetcher block is responsible for initiating as well as controlling the order of the transfer of data from the swath buffer to the internal ram of the bit rotation block. there are several control signals provided to the swath fetcher dma channel for controlling what order the channel will read data out of image memory. the fetcher dma will not support burst mode. this is due to the fact that in order to use burst mode, the dram that comprises the image memory must be accessed using page mode. when accessing dram for the bit rotation block, the sequential data stream rarely contains elements out of the same page of dram. because of this, in most cases, only single-access cycles can be realized when reading data out of the image memory for the bit rotation block. the order in which data is fetched out of the swath buffer depends on shuttle direction only. the way data is fetched out of the swath buffer is best described pictorially. in the figure, each cell corresponds to a halfword (16 bits) in memory. the gray portion represents the printable image region, and a full line corresponds to the warp of the swath buffer. the general order in which halfwords are fetched from the swath buffer is indicated by the arrows. the starting address value that the firmware must program into the swath fetcher dma channel depends on the shuttle direction. while printing in a left-to-right fashion (when viewing the print on the page), the value must correspond to the halfword of the upper left-hand corner of the image in the swath buffer (in the example shown, this address would be base+6h. while printing in a right-to-left fashion, the value must correspond to the upper right-hand corner of the image (in the figure, this would be base+ah). the value that would be programmed in the rotation line length (rotline) register in this example would be 0005h (one less than the actual number of bytes that comprise the image). base+5*warp base+3*warp base+warp-2h base+2h base+ch base+ah base+8h base+6h base+4h base+2h base+ch base+ah base+8h base+6h base+4h base base+warp base+(ng-1)*warp base+4*warp base+2*warp base base+warp base+(ng-1)*warp base+4*warp base+2*warp base+3*warp base+5*warp base+warp-2h left-to-right shuttle direction fetch order right-to-left shuttle direction fetch order figure 11-5. fetcher dma channel fetch order
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 11-5 11.2.2 bit packer the bit packer block is responsible for performing the actual rotation of the image data. it accomplishes this task by ?picking? the bits out of the internal bit rotation ram one bit at a time and packing them into the appropriate format such that the final output image is rotated 90 degrees. the bit packer circuits also contain the bit counter that describes the total number of printable bytes contained in the swath. the overall control of the print operation is controlled by this block. the parameters that are required by this block are: the line length (ll), the nozzle number (nn), the shuttle direction, and the packing order. in addition, this circuit also detects when there is an underrun condition. an underrun condition occurs when the system is not able to keep up with the print rate. finally, the interface to the external print asic is provided by this block. 11.2.3 local bit rotation ram this memory is 512x16. functionally, this memory consists of 2 banks of 256x16 memories, and only one of these buffers is used at a time for rotating image memory data. the double-buffering is used for reasons of system performance. when using the double-buffering mechanism, the system only needs to transfer the data at a rate that corresponds to the print rate. this is due to the fact that while one bank is being loaded with swath data, the other bank is being operated upon, or rotated and shipped to the external print asic. this memory is accessible by three resources: the siu, the swath fetcher, and the bit packer. when a bit rotation operation is in progress (when rotatestart in the rotctrl register is set to 1), then the siu may not access this memory. during this time, both the swath fetcher and the bit packer may access this memory, but not the same bank simultaneously. when no bit rotation operation is in progress (the rotatestart bit is set to 0), then only the siu has access to this memory through address locations 01ff9000h-01ff93ffh. 11.2.4 brb local sram memory controller (brb_memif) the brb_memif block is responsible for controlling all accesses to local brb sram. during bit rotation operation, it will lock out all siu accesses. at this time, it will allow both the bit packer and the swath fetcher blocks to access the sram. the swath fetcher block is a write-only resource, and the bit packer is a read-only resource. arbitration to the sram by each of these resources is controlled with a rotating priority to ensure that neither the swath fetcher or the bit packer get locked out for any length of time. 11.2.5 control, status, and data registers (brb_regs) this block provides all required registers used in bit rotation operation. these registers are described in detail later in section 11.3. the functional registers are spilt into two separate areas: operation registers, and setup registers. the operation registers are those registers that are meant for access during bit rotation. the setup registers are those register that are intended to be used once to set up the next print swath for printing. the operation registers for the bit rotation block are located at 01ff8060h-01ff806fh, however, only locations 01ff8060h-01ff8063h are used. the setup registers are located at 01ff8870h-01ff888fh, however, only locations 01ff8870h-01ff8875h are used. the registers are summarized. register address register name summarized description 01ff8060h rotation control - rotctl provides programmability of parameters, initiates rotation, and provides status. 01ff8874h rotation line length - rotline contains the value of the line length in terms of bytes. 01ff8870h nozzle number - rotnn provides programmability of number of nozzles on inkjet head. 01ff8872h brb warp - brbwarp provides programmability of swath warp in increments of 32 bytes, up to 4096 bytes. 01ff8062h packing register - rotpack provides the data for the external print asic
MFC2000 multifunctional peripheral controller 2000 hardware description 11-6 conexant 100723a 11.2.6 brb synchronization the swath fetcher and the brb_regs blocks operate at siuclk frequencies, while the brb_memif, and the bit packer circuits operate at ihsclk frequencies. the reason for this is to control power consumption and noise, as the higher siuclk frequency is not required for operation of the bit packer and the brb local sram controller. because of these different frequencies, a synchronization block is required to allow these blocks to communicate in a reliable fashion. 11.3 register description rotation control register address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default rotation control register ( rotctrl) 01ff8061 rotate start (w) rotate status (r), 1:busy (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value 0xxxxxxxb read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default rotation control register ( rotctrl) 01ff8060 (not used) (not used) (not used) (not used) packing order 0: odd then even 1: even then odd underrun 0: no underrun 1: underrun occurred. packed-byte status 0: not ready 1: ready shuttle direction 0: left to right 1: right to left rst. value xxxx0000b read value 00h bit 15 to start the bit rotation function, the cpu should write a 1 to this bit location. reading this bit location indicates the status of the block rotation function. 0 = not busy, 1 = busy. this bit will be set to 0 at the end of a print swath, and all bit rotation circuits will be reset with the exception of the brb registers. if an unrecoverable error condition occurs within the system, then the brb block may be reset by creating a falling edge on the rotatestart bit. bit 14-4 not used bit 3 the packing order allows the order of the groups of odd and even bits to be switched. bit 3 = 0 => odd bit is output first. bit 15 x x x x x x x x x x x x x x n18 n17 n16 n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 bit 0 18 nozzles 2nd dma ch2 halfword 1st dma ch2 halfword bit 3 = 1 => even bit is output first
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 11-7 bit 15 x x x x x x x x x x x x x x n17 n18 n15 n16 n13 n14 n11 n12 n9 n10 n7 n8 n5 n6 n3 n4 n1 n2 bit 0 18 nozzles 2nd dma ch2 halfword 1st dma ch2 halfword bit2 this bit indicates whether a print underrun condition has occurred. basically, an underrun condition exists if the system is not able to keep up with the print rate. bit 1 once a halfword has been packed and is ready for output to dma channel 2, a 1 will be indicated in this bit of the register. this bit directly reflects the state of the output signal brb_ch2rdy, and is intended only for status purposes. once the data has been read, the bit is cleared automatically. the bit is also reset by creating a falling edge on the rotatestart bit. bit 0 this bit is written by the cpu and indicates which direction the print head is moving as viewed when looking at the print on the page. 0 = left to right shuttle motion 1 = right to left shuttle motion rotation line length register address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default rotation line length register (rotlinelength) 01ff8875 (not used) (not used) (not used) (not used) (not used) ll10 ll9 ll8 rst. value xxxxx000b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default rotation line length register (rotlinelength) 01ff8874 ll7 ll6 ll5 ll4 ll3 ll2 ll1 ll0 rst. value 00h read value 00h bits 15-11 not used bits 10-0 the value in this field indicates the length in bytes of the actual printable data. the value programmed into this register is one less than the actual value in bytes. the printable data in a swath can be between 1 and 2048 bytes.
MFC2000 multifunctional peripheral controller 2000 hardware description 11-8 conexant 100723a rotation nozzle number register address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default rotation nozzle number register (rotnn) 01ff8871 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default rotation nozzle number register (rotnn) 01ff8870 nn7 nn6 nn5 nn4 nn3 nn2 nn1 nn0 rst. value 00h read value 00h bits 15-8 not used bits 7-0 this value describes the total number of nozzles on the inkjet head. the value written into this register is one less than the actual number of physical nozzles. the total number of nozzles that can be supported is between 1 and 256. brb warp address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default brb warp register (brbwarp) 01ff8873 (not used) (not used) (not used) (not used) bw11 bw10 bw9 bw8 rst. value xxxx0000b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default brb warp register (brbwarp) 01ff8872 bw7 bw6 bw5 (not used) (not used) (not used) (not used) (not used) rst. value 000xxxxxb read value 00h bits 15-12 not used bits 11-5 these bits are used to define the warp of the swath, or the actual jump line size. the smallest resolution of the warp is 32 bytes. the value that is written into this register is the actual value that will be used in the jump. the warp value can range from 0000h to 0fe0h. bits 4-0 not used
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 11-9 packing register address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default rotation packed data register (rotpackeddata) 01ff8063 rp15 rp14 rp13 rp12 rp11 rp10 rp9 rp8 rst. value 00h read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default rotation packed data register (rotpackeddata) 01ff8062 rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 rst. value 00h read value 00h bits 15-0 this register shows the contents of the halfword content that will be sent to the external print asic via the bit packer dma controller channel.
MFC2000 multifunctional peripheral controller 2000 hardware description 11-10 conexant 100723a 11.4 firmware operation 11.4.1 bit rotation setup and operation the following describes how to setup and operate the bit rotation block for printing of image swaths. the following example assumes that there is a 8mbyte dram residing in bank 0 of the system in question. it is also assumed that the swath buffer that resides in this dram is located at the base address of this device and grows up. since the memory grows down from address 03000000h, the base address for the dram is at 02800000. in addition, i am assuming that the image that is to be printed is 72 bytes wide, has a warp of 96 bytes, shuttle direction is right-to-left, and the number of nozzles is 56. program the dma controller - channel 2 and 3 1. program the address of the bit rotation packing register (01ff8062h) into the dma high address counter (01ff818ah) and the dmacnt2lo (01ff8188h) and the dma2cnthi (01ff818ah) registers: (dmacnt2lo) <= 8062h; (dmacnt2hi) <= 01ffh; 2. program the dma2config register (01ff81b2h). it must know that it is being used for bit rotation as well as for reads and halfword mode: (dma2config) <= 0180h; 3. program the dma channel 2 block size. here, we set up for unlimited block size. bit 15 is the enable bit for this channel. (dma2blksize) <= 8000h; 4. the only registers that you need to program the dma channel 3 controller with is the address of the image memory: since the shuttle direction is right-to-left, we must initialize these registers with the upper right-hand corner of the swath buffer. (dma3cntlo) <= 0046h; (dmacnt3hi) <= 0280h; program the brb 1. first, load the rotation line length register (rotline - 01ff8874h) with one less than the length of the image which would be 72 bytes - 1 = 71 = 47h. (rotline) <= 0047h; 2. program the brbwarp (01ff8872h) register with the actual warp value. here, the warp is 96 bytes = 60h. (brbwarp) <= 0060h; 3. program the nozzle number into rotnn (01ff8870h) with the number of nozzles -1. in this case, the actual number of nozzles is 56. so, we need to program the rotnn with 56 - 1 = 55 = 37h. (rotnn) <= 0037h; 4. program the rotctrl (01ff8060h) with the proper value. in this case, the shuttle direction is right-to-left. (rotctrl) <= 8001h; once the rotation bit has been set, then bit rotation starts. the status bit (bit 15 of rotctrl) may then be polled to determine when the swath is completed with printing. on the next shuttle stroke, only the address in channel 3 of the dma controller needs to be changed as well as the shuttle direction bit within the rotctrl register. these should be the only parameters that need to change, once the initial parameters have been set up.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 11-11 11.4.2 swath loader requirements (software issues) due to the fact that the color nozzles are staggered as well as the fact that there is a physical separation vp of the color groups themselves, there are very special requirements imposed on the swath loader. in a situation where the mode is black only, then a minimum of two block buffers within image memory are required. this is due to the fact that while one block buffer is being printed, the other buffer may be simultaneously filled by the image loader. color mode is quite different from black-only print mode. in color mode, three separate colors are used: yellow, magenta, and cyan. the order of these colors may differ from one printhead to another. this is why the colors have been assigned simply as ?color1?, ?color2?, and ?color3? in figure 11-1. on the first print swath of a page, color3 is printed. on the next print block, color3, and ng-vp + 1 nozzles of color2 are printed. on the third pass, color3, color2, and ng-(2*vp) + 1 nozzles of color1 are fired. in looking at this pattern, we see that two buffers are required to deal with printing color3 (one block history required), three buffers are required in printing color2 (two block history required), and four buffers are required in printing color1 (three block history required). peerless pcl has a limitation that the color blocks that comprise the image data cannot be easily split up in order to take into account the vp parameter. the color data must be contiguous within the blocks. due to this fact (along with the fact that the cpu may need to perform some preprocessing of the image prior to printing), the color buffers that are provided for use by the bit rotation block are prepared by the cpu in the background. the figure shows the typical preparation of these buffers in the background by the cpu. note: before scanning starts, the two prepared color buffers must be zero-filled by the cpu for reasons of top-of-page boundary conditions. if, at the end of the printed page, there are fewer lines than the number in the prepared buffers, then the remainder of the prepared buffers must be zero-filled to account for bottom-of-page boundary conditions.
MFC2000 multifunctional peripheral controller 2000 hardware description 11-12 conexant 100723a data buffers dynamically allocated by cpu two buffers prepared in background by cpu color 3, buffer 0, lines 0 to ng color 2, buffer 0 lines ng-vp+1 to ng color 2, buffer 1 lines 0 to ng-vp lines 0 to (2*vp) - 1 are zero-filled. color 1, buffer 0, lines 0 to ng - (2*vp) . color 3, buffer 1, lines 0 to ng color 2, buffer 1, lines ng - (vp+1) to ng. color 2, buffer 2, lines 0 to ng-vp. color 1, buffer 0, lines ng - (2*vp) + 1 to ng. color 1, buffer 1, lines 0 to ng - (2*vp) . note: this example shows what these buffers should look like if printing swaths 3 and 4 starting with swath 1. note: ng is one less than the physical number of nozzles in the color group. vp is the vertical distance between nozzle groups color1, buffer 3 color1, buffer 2 color1, buffer 1 color1, buffer 0 color 2, buffer 2 color2, buffer 1 color2, buffer 0 color3, buffer 0 color3, buffer 1 note: each buffer is ng lines deep for swath 3 for swath 4 figure 11-6. cpu background print data preparation during black-only printing, the two buffers that are prepared for color printing simply become the two buffers that are used for the black-only print mode. each of these buffers will contain as many lines as there are nozzles on the printhead. image format the data that is presented to the bit rotation block is always in little-endian format. the data within the system is in 2 separate formats: big-endian and little-endian. however, if the data in image memory is in big-endian format, then the siu will translate that data to a little-endian format during the dma operation with the endian conversion bit enabled, to ensure that the bit rotation block only needs to deal with little-endian formatted data. the little endian format that the bit rotation block expects to see is shown in the following illustration:
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 11-13 image memory increasing addresses p0 p7 byte 0 byte 1 byte 2 byte 3 p8 p15 p16 p23 p24 p31 b7 b0 b7 b0 b7 b0 b7 b0 amfc little- endian format byte linesize byte linesize*2 byte 4 b7 b0 p32 p47 0 figure 11-7. MFC2000 little-endian format
MFC2000 multifunctional peripheral controller 2000 hardware description 11-14 conexant 100723a this page is intentionally blank
multifunctional peripheral controller 2000 MFC2000 100723a conexant 12-1 12. printer and scanner stepper motor interface 12.1 vertical print stepper motor interface 12.1.1 vertical print stepper motor control description the stepper motor can be controlled by this block to run at constant speed, increasing speed (acceleration), or decreasing speed (deceleration). the control logic is based on a loadable step timer and a step timer register. a pulse and interrupt are generated when the step timer expires (timed-out) and at the same time, the content of the step timer register is automatically loaded into the step timer. the pulse is used to change the phase pattern to the next one in the motor pattern control sub-block and the interrupt is used to inform cpu to load the new step timer value to the step timer register if necessary for the step after the next step (see figure 12-1). motor pattern control motor timer stepclk divider motor external motor driver the vertical printer motor control block motor moving clock (mmclk) stepping clock (stepclk) stepping pulse (steppulse) vertical print stepping interrupt (vpstepirq) internal bus interface and vpm logic control MFC2000 chip external circuit vpm_pwrctrl figure 12-1. vertical printer motor control block diagram the printer motor control lines are the four pins pm[3:0]/gpo[3:0]. these pins are selected as printer motor control lines when bit 0 in the gpioconfig register is set to 0 (default), and are selected as gpo's when this bit is set to 1. the printer pattern or gpo data is output on pins pm[3:0]/gpo[3:0] from bits [3:0] (vpmf[3:0]) of the vpmpattern register. when selected as gpo's, data written by cpu to the vpmpattern register is immediately output on the gpo pins and output data are not changed unless cpu writes another new data to the vpmpattern register. when selected as printer motor control lines, data is not allowed to be written to the vpmpattern register no matter whether the motor stepping is disabled or enabled. at the beginning of the motor moving process, cpu needs to write the stepping mode and the stepping direction to the vpstepctrl register, the initial vertical print motor pattern to the vpmpattern register, and the 1st step timer value to the vpsteptimer register (used to define the time interval between enabling stepping and the 1st step).
MFC2000 multifunctional peripheral controller 2000 hardware description 12-2 conexant 100723a caution: the vertical print motor pattern register (vpmpattern register) can only be written when it is used as the gpo function. in other words, bit 0 of the gpioconfig register is set to 1. then, cpu sets bit 0 of the gpioconfig register to 0 and enables the vertical print motor stepping. the content (the 1st step timer value) of the step timer register is automatically loaded into the step timer and at the same time an interrupt is generated (the step pulse is blocked at this time). cpu writes the 2nd step timer value into the step timer register in the stepping interrupt routine. when the step timer expires (timed-out), a pulse is generated to change the phase pattern to the next one (the 1st step) and the content (the 2nd step timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated to inform cpu to load the 3rd step timer value to the step timer register. at the near end of the motor stepping, a pulse is generated to change the phase pattern to the next one (the ?n-2? step, n: the last step) and the content of the step timer register (the time interval between the ?n-2? and ?n-1 steps) is automatically loaded into the step timer and an interrupt is generated to inform cpu to load the last step timer value to the step timer register when the step timer expires (timed-out). when the step timer expires again (timed- out), a pulse is generated to change the phase pattern to the next one (the ?n-1? step) and the content (the last step timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated to inform cpu to load the large dummy timer value to the step timer register. finally, a pulse is generated to change the phase pattern to the next one (the last step) and the content (the large dummy timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated to inform cpu to disable the motor stepping. the step timer is cleared to 0 and the stepping pulse is blocked immediately after cpu disables the motor stepping. the step enable bit in the vpstepctrl register only controls if the motor pattern is allowed to change to the next one. the motor pattern in the vpmpattern register always goes out. cpu has the responsibility to write value ?00h? to the vpmpattern register or set bit 4 of the vpstepctrl register to a proper value according to the external power control circuit for not driving the vertical print motor. bit 4 value of the vpstepctrl register directly goes out of the MFC2000 chip through the gpio[13]/sastxd/pmpwrctrl pin. caution: the gpio[13]/sastxd/pmpwrctrl pin can only be used as the pmpwrctrl pin when bit11 of the gpioconfig1 register is ?0? and bit 12 of the gpioconfig1 register is ?1?. the time interval between two adjacent stepping pulses (for example, t1 and t2) is determined by the timer value. the min. time difference between two adjacent stepping pulses (it is called the timer resolution, for example, ? t = | t2-t1|.) is determined by the frequency of the stepping clock (see figure 12-2). time is controlled by the step timer steppulse (in the speed-up period) t1 t2 figure 12-2. stepping timing
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 12-3 the change sequence of the phase pattern in the motor pattern control sub-block is as follows: after the cpu gives the initial phase pattern (any column in the following tables), the phase pattern will automatically change to the next one after getting the time-out pulse of the timer (the stepping pulse) according to the clockwise (cw) or counterclockwise (ccw) rotation in the following tables. table 12-1. full step/single phase excitation ------------------------- > cw rotation step pattern 1 step pattern 2 step pattern 3 step pattern 4 step pattern 1 vpm [0](phase a) 10001 vpm [1](phase b) 01000 vpm [2](phase c) 00100 vpm [3](phase d) 00010 < ------------------------ ccw rotation table 12-2. full step/two phase excitation ------------------------- > cw rotation step pattern 1 step pattern 2 step pattern 3 step pattern 4 step pattern 1 vpm [0](phase a) 10011 vpm [1](phase b) 11001 vpm [2](phase c) 01100 vpm [3](phase d) 00110 < ------------------------ ccw rotation table 12-3. half-step excitation ------------------------- > cw rotation step fp1 step hp2 step fp3 step hp4 step fp5 step hp6 step fp7 step hp8 vpm [0] 1 0 0 0 0 0 1 1 vpm [1] 1 1 1 0 0 0 0 0 vpm [2] 0 0 1 1 1 0 0 0 vpm [3] 0 0 0 0 1 1 1 0 < ------------------------ ccw rotation note: fpx: full step pattern and x: 1-4, hpx: half step pattern and x:1-4 programmability: ? the frequency of stepclk is programmable (around 1.25 mhz ? 39 khz) if the iclk (internal) frequency is 10 mhz. ? the step timer value is programmable (around 1us ? 400ms) if the iclk (internal) frequency is 10 mhz. ? the motor moving direction (clockwise or counterclockwise) and the stepping mode (full step or half step) is programmable. ? the motor phase pattern is programmable. ? control bits for clearing the stepping interrupt and enabling the stepping logic are included. ? a control bit for the vertical print motor power on/off.
MFC2000 multifunctional peripheral controller 2000 hardware description 12-4 conexant 100723a 12.1.2 register description address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: vertical printer motor pattern register (vpmpattern) 01ff805d (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: vertical printer motor pattern register (vpmpattern) 01ff805c vpmh[3] vpmh[2] vpmh[1] vpmh[0] vpmf[3] vpmf[2] vpmf[1] vpmf[0] rst. value 00h read value 00h for the full step excitation, the phase pattern vpm[3:0] (see table 12-1 and table 12-2) needs to be put into vpmf[3:0] of this vpmpattern register. bit[7:4] of this register are ?don?t care?. for the half step excitation, two adjacent phase patterns (see table 12-3) need to be put into the vpmpattern register: vpm[3:0] at fp[x] column needs to be put into vpmf[3:0] and vpm[3:0] at hp[x] column needs to be put into vpmh[3:0]. the current output at pm[3:0] is vpmf[3:0]. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: step clock register (vpstepclk) 01ff8853 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: step clock register (vpstepclk) 01ff8852 (not used) (not used) (not used) bit 4 of the step clock divider bit 3 of the step clock divider bit 2 of the step clock divider bit 1 of the step clock divider bit 0 of the step clock divider rst. value xxx00000b read value 00h ? stepclk = iclk/(8 * (n+1)), n (bit[4:0] of the step clock divider): from 0 to 31 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: step control register (vpstepctrl) 01ff8059 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: step control register (vpstepctrl) 01ff8058 (not used) (not used) (not used) vertical print motor power control stepping mode 0: full step 1: half step motor direction 0: cw 1: ccw step enable 0: disable 1: enable stepirq clear 1:clear rst. value xxx00000b read value 00h
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 12-5 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: step timer register (vpsteptimer) 01ff805b (not used) (not used) bit 13 of the step timer bit 12 of the step timer bit 11 of the step timer bit 10 of the step timer bit 9 of the step timer bit 8 of the step timer rst. value xx000000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: step timer register (vpsteptimer) 01ff805a bit 7 of the step timer bit 6 of the step timer bit 5 of the step timer bit 4 of the step timer bit 3 of the step timer bit 2 of the step timer bit 1 of the step timer bit 0 of the step timer rst. value 00h read value 00h ? the time interval between two adjacent step pulses = (n+1)/stepclk, n (bit[13:0] of the step timer): from 0 to 16383 12.2 scanner stepper motor interface 12.2.1 scanner stepper motor control description the stepper motor can be controlled by this block to run at constant speed, increasing speed (acceleration), or decreasing speed (deceleration). the motor timer sub-block contains two sets of loadable timers and timer registers. one is used for the step control logic and the other is used for the delay control logic. the step control logic is based on a loadable step timer and a step timer register. a pulse and interrupt are generated when the step timer expires (timed-out) and at the same time, the content of the step timer register is automatically loaded into the step timer. the pulse is used to change the phase pattern to the next one in the motor pattern control sub-block and the interrupt is used to inform cpu to load the new step timer value to the timer register if necessary for the step after the next step (see figure 12-3). motor pattern control motor timer stepclk divider motor external motor driver the scan motor control block motor moving clock (mmclk) stepping clock (stepclk) stepping pulse (steppulse) vertical print stepping interrupt (sstepirq) internal bus interface and sm logic control MFC2000 chip external circuit sm_pwrctrl msint0 figure 12-3. scan motor control diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 12-6 conexant 100723a the scan motor stepping needs to synchronize to the scan cycle during scanning. signal msint0 is used to indicate the beginning of the scan cycle. msint0 synchronization can be enabled or disabled through the register setting. this is the main difference between the vertical print motor control block and the scan motor control block. the delay control logic is based on a loadable delay timer and a delay timer register. the msint0 and the delay timer control when the motor timer sub-block sends out the first stepping pulse after cpu enables the scan motor stepping. once, cpu enables the scan motor stepping, the motor timer sub-block waits for the msint0 pulse to load the delay timer value from the delay timer register and activate the delay timer if the msint0 synchronization is enabled. otherwise, the motor timer sub-block loads the new timer value from the delay timer register and activates the delay timer immediately. the first stepping pulse will be sent to the motor pattern control sub-block when the delay timer expires (timed-out). the delay timer only works once after cpu enables the scan motor stepping for the first step. the scan motor control lines are the four pins sm[3:0]/gpo[7:4]. these pins are selected as scanner motor control lines when bit 1 in the gpioconfig register is set to 0 (default), and are selected as gpo's when this bit is set to 1. the scanner motor pattern or gpo data is output on pins sm[3:0]/gpo[7:4] from bits [3:0] of the smpattern register. when selected as gpo's, data written by cpu to the smpattern register is immediately output on the gpo pins and output data are not changed unless cpu writes another new data to the smpattern register. when selected as scanner motor control lines, data is not allowed to be written to the smpattern register no matter whether the motor stepping is disabled or enabled. caution: the vertical print motor pattern register (smpattern register) can only be written when it is used as the gpo function. in other words, bit 1 of the gpioconfig register is set to 1. at the beginning of the motor moving process, cpu needs to write the stepping mode and the stepping direction to the sstepctrl register, the initial scan motor pattern to the smpattern register, the delay timer value to the sdelaytimer register, and the 1st step timer value to the ssteptimer register (used to define the time interval between the 1st and 2nd steps). then, cpu sets bit 1 of the gpioconfig register to 0 and enables the scan motor stepping. if the msint0 synchronization is disabled, the content of the delay timer register is immediately loaded into the step timer. if the msint0 synchronization is enabled, the delay timer loading will be delayed until the beginning of the scan (seeing the msint0 pulse). after motor timer sub-block loads the new timer value from the delay timer register, it activates the delay timer immediately. the first stepping pulse will be sent to the motor pattern control sub-block when the delay timer expires (timed-out). at the same time, the content (the 1st step timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated. cpu writes the 2nd step timer value into the step timer register in the stepping interrupt routine. when the step timer expires (timed-out), a pulse is generated to change the phase pattern to the next one (the 2nd step) and the content (the 2nd step timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated to inform cpu to load the 3rd step timer value to the step timer register. at the end of the motor stepping, a pulse is generated to change the phase pattern to the next one (the ?n-2? step, n: the last step) and the content of the step timer register (the time interval between the ?n-2? and ?n-1 steps) is automatically loaded into the step timer and an interrupt is generated to inform cpu to load the last step timer value to the step timer register when the step timer expires (timed-out). when the step timer expires again (timed- out), a pulse is generated to change the phase pattern to the next one (the ?n-1? step) and the content (the last step timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated an interrupt is generated to inform cpu to load the large dummy timer value to the step timer register. finally, a pulse is generated to change the phase pattern to the next one (the last step) and the content (the large dummy timer value) of the step timer register is automatically loaded into the step timer and an interrupt is generated to inform cpu to disable the motor stepping. the step and delay timers are cleared to 0 and the stepping pulse is blocked immediately after cpu disables the motor stepping.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 12-7 the step enable bit in the sstepctrl register only controls if the motor pattern is allowed to change to the next one. the motor pattern in the smpattern register always goes out. cpu has the responsibility to write value ?00h? to the smpattern register or set the bit 5 of the sstepctrl register to a proper value according to the external motor power control circuit for not driving the scan motor. bit 5 value of the sstepctrl register directly goes out of the MFC2000 chip through the gpio[12]/sasclk/smpwrctrl pin. caution: the gpio[12]/sasclk/smpwrctrl pin can only be used as the smpwrctrl pin when bit 9 of the gpioconfig1 register is ?0? and bit 10 of the gpioconfig1 register is ?1?. the step time interval between two adjacent stepping pulses (for example, t1 and t2) is determined by the timer value. the min. time difference between two adjacent stepping pulses (it is called the timer resolution, for example, ? t = | t2-t1|.) is determined by the frequency of the stepping clock (see figure 12-4). time is controlled by the step timer steppulse (in the speed-up period) t1 t2 figure 12-4. stepping timing the change sequence of the phase pattern in the motor pattern control sub-block is as follows: after the cpu gives the initial phase pattern (any column in the following tables), the phase pattern will automatically change to the next one after getting the time-out pulse of the timer (the stepping pulse) according to the clockwise (cw) or counterclockwise (ccw) rotation in the following tables. table 12-4. full step/single phase excitation ------------------------- > cw rotation step pattern 1 step pattern 2 step pattern 3 step pattern 4 step pattern 1 sm [0](phase a)10001 sm [1](phase b)01000 sm [2](phase c)00100 sm [3](phase d)00010 < ------------------------ ccw rotation table 12-5. full step/two phase excitation ------------------------- > cw rotation step pattern 1 step pattern 2 step pattern 3 step pattern 4 step pattern 1 sm [0](phase a)10011 sm [1](phase b)11001 sm [2](phase c)01100 sm [3](phase d)00110 < ------------------------ ccw rotation
MFC2000 multifunctional peripheral controller 2000 hardware description 12-8 conexant 100723a table 12-6. half-step excitation ------------------------- > cw rotation step fp1 step hp2 step fp3 step hp4 step fp5 step hp6 step fp7 step hp8 sm [0] 1 0 0 0 0 0 1 1 sm [1] 1 1 1 0 0 0 0 0 sm [2] 0 0 1 1 1 0 0 0 sm [3] 0 0 0 0 1 1 1 0 < ------------------------ ccw rotation note: fpx: full step pattern and x: 1-4, hpx: half step pattern and x:1-4 programmability: ? the frequency of stepclk is programmable (around 1.25 mhz ? 39 khz) if the iclk (internal) frequency is 10 mhz. ? the step timer value is programmable (around 1us ? 400ms) if the iclk (internal) frequency is 10 mhz. ? the delay timer value is programmable (around 1us ? 400ms). ? the motor moving direction (clockwise or counterclockwise) and the stepping mode (full step or half step) is programmable. ? the motor phase pattern is programmable. ? control bits for clearing the stepping interrupt and enabling the stepping logic are included. ? the msint0 synchronization can be enabled and disabled. ? a control bit for the scan motor power on/off.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 12-9 12.2.2 scan motor current control the current control logic is added to this block. two current control output signals (smi[1:0]) are needed to control 4 different current modes. three different current modes can be used within the time period of one step (see figure 12-5). t1 and t2 are programmable in one step period. the current mode in each current period of one step period is programmable. cpu can load t1 and t2 values and current modes of three current periods within one step for the next step at the same time when cpu loads the next step timer value by using the scan step interrupt (sstepirq). in other words, t1, t2, and current modes are double buffered. smi[0] output value is 1 and smi[1] output value is 1 after reset and when sm[3:0] pins are used as gpo?s. the default current mode is also programmable when sm[3:0] pins are used as motor control pins and motor stepping is disabled. changing step pattern (stepping to the next step) one step period one step period one step period different current modes different current modes different current modes t1 t2 t1 t1 t2 t2 figure 12-5: current control diagram two current control signals (smi1 and smi0) share same pins with pm[3]/gpo[3] and pm[2]/gpo[2]. there is a smi[1:0] output select bit in the sstepctrl register to select which signals output on pm[3:2] pins. 12.2.3 register description address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: scanner motor pattern register (smpattern) 01ff8057 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: scanner motor pattern register (smpattern) 01ff8056 smh[3] smh[2] smh[1] smh[0] smf[3] smf[2] smf[1] smf[0] rst. value 00h read value 00h for the full step excitation, the phase pattern sm[3:0] (see table 12-4 and table 12-5) needs to be put into smf[3:0] of this smpattern register. bit[7:4] of this register are ?don?t care?. for the half step excitation, two adjacent phase patterns (see table 12-6) need to be put into the smpattern register: sm[3:0] at fp[x] column needs to be put into smf[3:0] and sm[3:0] at hp[x] column needs to be put into smh[7:4]. the current output at pm[3:0] is smf[3:0].
MFC2000 multifunctional peripheral controller 2000 hardware description 12-10 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: step clock register (sstepclk) 01ff8851 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: step clock register (sstepclk) 01ff8850 (not used) (not used) (not used) bit 4 of the step clock divider bit 3 of the step clock divider bit 2 of the step clock divider bit 1 of the step clock divider bit 0 of the step clock divider rst. value xxx00000b read value 00h ? stepclk = iclk/(8 * (n+1)), n (bit[4:0] of the step clock divider): from 0 to 31 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: step control register (sstepctrl) 01ff8051 i31 i30 i21 i20 i11 i10 di1 di0 rst. value ffh read value ffh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: step control register (sstepctrl) 01ff8050 (not used) smi output select scan motor power control msint0 sync 0: disabled 1: enabled stepping mode 0: full step 1: half step motor direction 0: cw 1: ccw step enable 0: disable 1: enable stepirq clear 1:clear rst. value x0000000b read value 00h bits 15-14 the third current control values go out to the scan current control pins (smi1 and smi0) within one step time period. bits 13-12 the second current control values go out to the scan current control pins (smi1 and smi0) within one step time period. bits 11-10 the first current control values go out to the scan current control pins (smi1 and smi0) within one step time period. bits 9-8 the default current control values go out to the scan current control pins (smi1 and smi0) when the motor stepping is disabled and sm[3:0] is used for motor control. bits 6 control which signal output to pm[3:2] pins (smi[1:0] output signals or pm[3]/gpo[3] and pm[2]/gpo[2] output signals). 0: output pm[3]/gpo[3] and pm[2]/gpo[2] signals, 1: output smi[1:0] signals. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: step timer register (ssteptimer) 01ff8053 (not used) (not used) bit 13 of the step timer bit 12 of the step timer bit 11 of the step timer bit 10 of the step timer bit 9 of the step timer bit 8 of the step timer rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: step timer register (ssteptimer) 01ff8052 bit 7 of the step timer bit 6 of the step timer bit 5 of the step timer bit 4 of the step timer bit 3 of the step timer bit 2 of the step timer bit 1 of the step timer bit 0 of the step timer rst. value 00h read value 00h ? the time interval between two adjacent step pulses = (n+1)/stepclk, n (bit[13:0] of the step timer): from 0 to 16383
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 12-11 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: step delay timer register (ssdelaytimer) 01ff8055 (not used) (not used) bit 13 of the delay timer bit 12 of the delay timer bit 11 of the delay timer bit 10 of the delay timer bit 9 of the delay timer bit 8 of the delay timer rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: step delay timer register (ssdelaytimer) 01ff8054 bit 7 of the delay timer bit 6 of the delay timer bit 5 of the delay timer bit 4 of the delay timer bit 3 of the delay timer bit 2 of the delay timer bit 1 of the delay timer bit 0 of the delay timer rst. value 00h read value 00h ? the delay time interval before stepping = (n+1)/stepclk, n (bit[13:0] of the step delay timer): from 0 to 16383 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: current timer 1 register (sscurtimer1) 01ff804d (not used) (not used) bit 13 of the current timer bit 12 of the current timer bit 11 of the current timer bit 10 of the current timer bit 9 of the current timer bit 8 of the current timer rst. value xx000000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: current timer 1 register (sscurtimer1) 01ff804c bit 7 of the current timer bit 6 of the current timer bit 5 of the current timer bit 4 of the current timer bit 3 of the current timer bit 2 of the current timer bit 1 of the current timer bit 0 of the current timer rst. value 00h read value 00h ? this register defines when to change the first driving current to the second driving current within one step time period. the current timer 1 value in this register must be less than the step timer value set in the ssteptimer register for the same step and greater than 0. otherwise, the current will not be changed. once the step timer counts down to the current timer 1 value, the current control signals changes to i20 and i21 from i10 and i11 in the sstepctrl register. i10 and i11 are the initial values of the current control signals within a step. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: current timer 2 register (sscurtimer2) 01ff804f (not used) (not used) bit 13 of the current timer bit 12 of the current timer bit 11 of the current timer bit 10 of the current timer bit 9 of the current timer bit 8 of the current timer rst. value xx000000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: current timer 2 register (sscurtimer2) 01ff804e bit 7 of the current timer bit 6 of the current timer bit 5 of the current timer bit 4 of the current timer bit 3 of the current timer bit 2 of the current timer bit 1 of the current timer bit 0 of the current timer rst. value 00h read value 00h ? this register defines when to change the second driving current to the third driving current within one step time period. the current timer 2 value in this register must be less than the current timer 1 value set in the sscurtimer1 register for the same step and greater than 0. otherwise, the current will not be changed. once the step timer counts down to the current timer 2 value, the current control signals changes to i30 and i31 from i20 and i21 in the sstepctrl register.
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multifunctional peripheral controller 2000 MFC2000 100723a conexant 13-1 13. general purpose inputs/outputs (gpio) 13.1 gpio signals the amfpc provides 31 gpio lines (gpio[30:0]) typically used for i/o control, each of which is multiplexed with other signals. the direction of each gpio line (input or output) is programmable using the hardware registers shown in section 13.3. gpio0 gpio0 is multiplexed with the flash memory write enable signal (fwrn) for the nand-type flash memory, this gpio0 pin is also multiplexed with w_rn. this pin is selected as a gpio when bit 2 of the gpioconfig1 register is set to 0 and emulator signals are not enabled, in this case, the direction of this pin is controlled by bit 0 of the gpiodir register. if gpiodir[0] is set to one, this pin will ouput the value of the bit 0 from gpiodata register, and, if gpiodir[0] is set to zero, the value of the gpio0 can be read back by reading gpiodata[0]. this pin is selected as fwrn when the gpioconfig1 bit is set to 1, in this case, this pin becomes an output pin regardless of the value in the gpiodir[0]. this pin is selected as w_rn when emusig_en is set to 1, refer to testmgr section for emusig_en signal definition. gpio1 gpio1 is multiplexed with the flash memory read enable signal (frdn) for the nand-type flash memory, this gpio1 pin is also multiplexed with xakn. this pin is selected as a gpio when bit 2 of the gpioconfig1register is set to 0 and, in this case, the direction of this pin is controlled by bit 1 of the gpiodir register. if gpiodir[1] is set to one, this pin will ouput the value of the bit 1 from gpiodata register, and, if gpiodir[1] is set to zero, the value of the gpio1 can be read back by reading gpiodata[1]. this pin is selected as fwrn when the gpioconfig1 bit is set to 1, in this case, this pin becomes an output pin regardless of the value in the gpiodir[1]. this pin is selecetd as xakn when emusig_en is set to 1, refer to testmgr section for emusig_en signal definition. gpio2 gpio2 is multiplexed with ssclk2, this pin is also used for the dma request input from dma channel 1 (dmareq1). if this pin is used as dmareq1, the direction of this pin needs to be set as input. if ssclk2 function is used, the bit 0 of gpioconfig2 register needs to be set to 1. if this pin is used as ssclk2, the gpio2 direction and data setting for this pin is no longer valid. when bit 16 of gpiocofig register is set to 0, this pin can be used as gpio2, in this case, the direction of this pin is controlled by bit 2 of the gpiodir register. the gpio2 input/output value is controlled by bit 2 of the gpiodata register.
MFC2000 multifunctional peripheral controller 2000 hardware description 13-2 conexant 100723a gpio3 gpio3 is multiplexed with the dma acknowledge of the dma channel 1 (dmaack1), it is also used as ssrxd2 input. if this pin is used as ssrxd2, the direction of this pin needs to be set as input and the dmaack1 function must be disabled. if this pin is used as dmaack1, the gpio direction and data setting for this pin is no longer valid. this function is enabled by setting extdma1sel to 1. if this pin is used as gpio, the direction of this pin is controlled by bit 3 of the gpiodir register. the gpio3 input/output value is controlled by bit 3 of the gpiodata register. gpio[7:4] gpio[7:4] are multiplexed with general chip selects on pins gpio7/cs5n, gpio6/cs4n, gpio5/cs3n, and gpio4/cs2n. these pins are selected as gpio when the corresponding bits in the gpioconfig1 register are set to 0. the direction of these pins is controlled by the bits 7-4 in the gpiodir register. the gpio[7:4] input/output values are controlled by the bits 7-4, respectively, of the gpiodata register. in addition, the gpio[5]/cs3n pin is also multiplexed with the pwm3 signal. see the register description in the pwm section for settings. gpio6 can also used as input pin for ev_clk and eadc_d[3], if this function is selected, the direction control for gpio6 must be set to 0. gpio8 gpio8 is multiplexed with sssta1 and sc_clk1/2b, this pin is also used as the interrupt request 11 (irq11) input. if this pin is used as irq11, the direction of this pin needs to be set as input. if this pin is not used as irq11, the interrupt channel 11 needs to be disabled by setting the irqenable register in the interrupt controller. if sssta1 function is selected, the bit 15 of gpioconfig1 register must be set to 1. to enable sc_clk1/2b function, bit 15 of gpioconfig1 must be set to 0 and bit 18 of this register set to 1. only when both bit15 and bit2 of the gpioconfig2 register are set to 0, the gpio8 pin is enabled as gpio. when gpio function is enabled, the direction of this pin is controlled by bit 8 of the gpiodir register. the gpio8 input/output value is controlled by bit 8 of the gpiodata register. gpio9 gpio9 is also used as the interrupt request 13 (irq13n) input or eadc_d[2] input. if this pin is used as irq13n or eadc_d[2], the direction of this pin needs to be set as input. if this pin is not used as irq13n, the interrupt channel 13 needs to be disabled by setting the irqenable register in the interrupt controller. the direction of this pin is controlled by bit 9 of the gpiodir register. the gpio9 input/output value is controlled by bit 9 of the gpiodata register.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 13-3 gpio10 gpio10 is multiplexed with the pwm[4] signal, this pin is also used for p80_pb3 as input. when p80_pb3 function is used, the direction of this pin needs to be set as input. this pin is selected as a gpio when bit 7 of the gpioconfig1 register is set to 0. the direction of this pin is controlled by bit 10 of the gpiodir register, and the input/output value is controlled by bit 10 of the gpiodata register. the pwm[4] function is enabled by setting bit 7 of the gpioconfig1 register to 1, additional control is required to use pwm[4], refer to pwm section for detail. gpio11 gpio11 is also used for the calling party control input (cpcin) pin and multiplexed with the alttone output signal on pin gpio11/cpcin/alttone. this pin is selected as a gpio by setting bit 8 of the gpioconfig1 register to 0. the direction of this pin is controlled by bit 11 in the gpiodir register, and the input/output value is controlled by bit 11 in the gpiodata register. the alttone output signal is selected by setting bit 8 of the gpioconfig1 register to 1 and setting bit 11 of the gpiodir register to 1. if this pin is used as the cpcin signal input pin, the bit 11 of the gpiodir register is set to 0. in addition, the gpio11/cpcin/alttone pin is also multiplexed with the pwm0 signal. see the register description in the pwm section for settings. gpio[14:12] gpio[14:12] are multiplexed with the scan/print motor power control output signals, the ringer output signal, and the sasif signals on pin gpio14/sasrxd/ringer, gpio13/sastxd/pmpwrctrl, and gpio12/sasclk/smpwrctrl. these pins are selected as a gpio by setting bit[12:9] in the gpioconfig1 register to zero. the direction of these pins are controlled by bit[14:12] of the gpiodir register, and the input/output value is controlled by bit[14:12] of the gpiodata register. these pins are selected as the sasif signals or ringer/pmpwrctrl/smpwrctrl signals by setting bit[14:9] in the gpioconfig1 register (refer to gpioconfig1 register description). firmware needs to program gpio[14:12] pins to use sasrxd, sastxd, and sasclk for the sync mode. if the async mode of sasif is used, firmware only needs to program gpio[14:13] pins to use sasrxd and sastxd. gpio[12] can be still used as gpio. gpio15 gpio15 is multiplexed with sc_clk1/2c signals, this pin is also used as irq16 input. if this pin is used as irq16, the direction of this pin needs to be set as input. if this pin is not used as irq16, the interrupt channel 16 needs to be disabled by setting the irqenable register in the interrupt controller. if sc_clk1/2c function is selected, the bit 3 of gpioconfig2 register must be set to 1. to enable gpio15 function, bit 3 of gpioconfig2 must be set to 0. when gpio function is enabled, the direction of this pin is controlled by bit 15 of the gpiodir register. the gpio15 input/output value is controlled by bit 15 of the gpiodata register.
MFC2000 multifunctional peripheral controller 2000 hardware description 13-4 conexant 100723a gpio[21:16] gpio[21:16] are multiplexed with six p80 modem ia signals; in addition, gpio19 can be used for mirqn input signal, and gpio20 is further multiplexed with mcsn. six p80 modem ia signals are m_txsin, m_clkin, m_rxout, m_sck, m_strobe and m_cntrl_sin, they are multiplexed with gpio16 through gpio21 respectively. the control signals of this multiplexing are extia_mode and extia_sel, they are generated from ssd_p80. when extia_mode is 1, the six p80modem signals will appear on the gpio pins, these signals can be used to either interface to data ia (when extia_sel is 0) or voice ia (when extia_sel is 1). when extia_mode is 0, the gpio[21:16] become gpio and they are controlled by gpiodir and gpiodata registers as usual except gpio20 can become mcsn if bit 5 gpioconfig2 is set to 1 and gpio19 can be used as mirqn input. gpio22 gpio22 is multiplexed with eadc_sample signals. if eadc_sample function is selected, the bit 6 of gpioconfig2 register must be set to 1. to enable gpio22 function, bit 6 of gpioconfig2 must be set to 0. when gpio function is enabled, the direction of this pin is controlled by bit 22 of the gpiodir register. the gpio22 input/output value is controlled by bit 22 of the gpiodata register. gpio[30:23] gpio[30:23] are multiplexed with piod[7:0] signals respectively; if gpio function is selected, bit 8 of gpioconfig2 register must be set to 1, else, piod function is selected. when gpio function is enabled, the direction of this pin is controlled by bit 30-23 of the gpiodir register. the gpio[30:23] input/output value is controlled by bit 30-23 of the gpiodata register.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 13-5 13.2 gpo/gpi signals the MFC2000 also provides eight gpo lines (gpo[7:0]), which are multiplexed with printer and scanner motor control signals. gpo[3:0] gpo[3:0] are multiplexed with the printer motor control lines on the four pins pm[3:0]/gpo[3:0]. these pins are selected as gpo's when bit 0 in the gpioconfig1 register is set to 1, and are selected as printer motor control lines when this bit is set to 0. when these pins are selected as gpo's, the gpo[3:0] output values are controlled by the lowest 4 bits in the vpmpattern register, and appear on the output pins immediately. gpo[7:4] gpo[7:4] are multiplexed with the scanner motor control lines on the four pins sm[3:0]/gpo[7:4]. these pins are selected as gpo's when bit 1 in the gpioconfig1 register is set to 1, and are selected as scanner motor control lines when this bit is set to 0. when these pins are selected as gpo's, the gpo[7:4] output values are controlled by the lowest 4 bits in the smpattern register, and appear on the output pins immediately. gpo[13:8] if the pio interface is not enabled, the pins for piodir, busy, ackn, slctout, pe and faultn will become gpio8-gpio13 respectively. these pins are selected as gpo function when bit8 of gpioconfig2 register is set to 1, otherwise, pio interface will be selected. the gpo[13:8] data is controlled by bit 5-0 of gpodata register. gpo[17:14] gpo[17:14] are multiplexed with ao3, ae3, ao2 and ae2 respectively, in addition, gpo14 is multiplexed with sstxd2 and gpo15 is with sssta2. the multiplexing selection is controlled by bit 0 and bit 1 of the gpioconfig2 register. when bit0 of the gpioconfig2 register is 1, the sstxd2/sssta2 function is selected, when bit 0 is 0 and bit 1 is 1, the gpo[17:14] function is enabled and the output value of the gpo[17:14] is controlled by bit 9-6 of gpodata register. to select ao[3:2]/ae[3:2], both bit 0 and bit 1 of the gpioconfig2 register must be 0. gpi[3:0] four pio interface input pins can be used as gpi when pio interface is not used, the value on these gpi pins can be read from bit 15-12 of the gpodata register.
MFC2000 multifunctional peripheral controller 2000 hardware description 13-6 conexant 100723a 13.3 gpio control and data registers address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: gpio configuration 1 (gpioconfig1) 01ff8831 0=gpio[8] 1=ssstat1 gpio[14] select bits gpio[13] select bits gpio[12] select bits 0=gpio11 1=alttone rst value xxx00000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: gpio configuration 1 (gpioconfig1) 01ff8830 0=gpio10 1= pwm4 enable 0=gpio7 1=cs5n 0=gpio6 1=cs4n 0=gpio5 1=cs3n 0=gpio4 1=cs2n 0=gpio[1:0] 1=frdn and fwrn 0=scan mot. sm[3:0] 1= gpo[7:4] select 0=prt mot. pm[3:0] 1= gpo[3:0] select rst value 00h read value 00h register description : gpio configuration1 register bit 14-13: gpio[14] or ringer or sasrxd is selected. bit 14 bit 13 the gpio[14]/ringer/sasrxd pin 0 0 gpio[14] 0 1 sasrxd 1 0 ringer 1 1 (not used) bit 12-11: gpio[13] or pmpwrctrl or sastxd is selected. bit 12 bit 11 the gpio[13]/pmpwrctrl/sastxd pin 0 0 gpio[13] 0 1 sastxd 1 0 pmpwrctrl 1 1 (not used) bit 10-9: gpio[12] or smpwrctrl or sasclk is selected. bit 10 bit 9 the gpio[12]/smpwrctrl/sasclk pin 0 0 gpio[12] 0 1 sasclk 1 0 smpwrctrl 1 1 (not used)
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 13-7 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: gpio configuration 2 (gpioconfig2) 01ff8833 not used not used not used not used 0=pio select 1=gpo[13:8 ]/gpio[30:2 3] rst value xxx00000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: gpio configuration 2 (gpioconfig2) 01ff8832 0=pm[1:0] 1= spi_sic/spi _sid 0=gpio22 1=eadc_s ample 0=gpio2 0 1=mcsn not used 0=gpio15 1=sc_clk1/ 2c 0=gpio8 1=sc_clk1/ 2b 0=ae[3:2]/ao [3:2] 1=gpo[17:14 ] select 0=gpio[3:2 ] 1= ss2 select rst value 00h read value 00h register description : gpio configuration2 register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: gpi/gpo data (gpodata) 01ff883d gpi3 data gpi2 data gpi1 data gpi0 data not used not used gpo17 data gpo16 data rst value 00000000b read value xxxx00xxb address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: gpi/gpo data (gpodata) 01ff883c gpo15 data gpo14 data gpo13 data gpo12 data gpo11 data gpo10 data gpo9 data gpo8 data rst value 00h read value xxh register description : gpo data register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: gpio data 1 (gpiodata1) 01ff8835 gpio15 data gpio14 data gpio13 data gpio12 data gpio11 data gpio10 data gpio9 data gpio8 data rst value x0000000b read value 0xxxxxxxb address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: gpio data 1 (gpiodata1) 01ff8834 gpio7 data gpio6 data gpio5 data gpio4 data gpio3 data gpio2 data gpio1 data gpio0 data rst value 00h read value xxh address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: gpio data 2 (gpiodata2) 01ff8837 (not used) gpio30 data gpio29 data gpio28 data gpio27 data gpio26 data gpio25 data gpio24 data rst value x0000000b read value 0xxxxxxxb address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: gpio data 2 (gpiodata2) 01ff8836 gpio23 data gpio22 data gpio21 data gpio20 data gpio19 data gpio18 data gpio17 data gpio016 data rst value 00h read value xxh register description : gpio data 1/2 register
MFC2000 multifunctional peripheral controller 2000 hardware description 13-8 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: gpio direction 1 (gpiodi1) 01ff8839 gpio15 0=in 1=out gpio14 0=in 1=out gpio13 0=in 1=out gpio12 0=in 1=out gpio11 0=in 1=out gpio10 0=in 1=out gpio9 0=in 1=out gpio8 0=in 1=out rst value x0000000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: gpio direction 1 (gpiodir1) 01ff8838 gpio7 0=in 1=out gpio6 0=in 1=out (must be set to 0 if sartsel=1) gpio5 0=in 1=out gpio4 0=in 1=out gpio3 0=in 1=out gpio2 0=in 1=out gpio1 0=in 1=out gpio0 0=in 1=out rst value 00h read value 00h address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: gpio direction 2 (gpiodir2) 01ff883b (not used) gpio30 0=in 1=out gpio29 0=in 1=out gpio28 0=in 1=out gpio27 0=in 1=out gpio126 0=in 1=out gpio25 0=in 1=out gpio24 0=in 1=out rst value x0000000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: gpio direction 2 (gpiodir2) 01ff883a gpio23 0=in 1=out gpio22 0=in 1=out gpio21 0=in 1=out gpio20 0=in 1=out gpio19 0=in 1=out gpio18 0=in 1=out gpio17 0=in 1=out gpio16 0=in 1=out rst value 00h read value 00h register description : gpio direction 1/2 register
multifunctional peripheral controller 2000 MFC2000 100723a conexant 14-1 14. compressor and decompressor 14.1 functional description the t.4 data compression/decompression process is primarily implemented in hardware within the MFC2000 (see figure 14-2). hardware provides compression and decompression of data within a line, and adds fill bits at the end of a line to cause the number of bits (coded plus fill) to be a multiple of 16 (halfword justified) for t.4 mh and mr. for coding (compression), firmware (t.4 subsystem task) appends end-of-line characters and, if required, fill bits to support the minimum line times of ccitt t.4. on the receive side, firmware passes the coded line to the t.4 hardware. data flow control, to prevent buffer overflow/underflow, is also the responsibility of the firmware. line times less than 5 msec per line are supported by the MFC2000s' t.4 hardware; the line time supported by the overall system depends on other system factors (e.g. resolution, concurrency, etc). t4 line lengths up to 2046 bytes are supported. there are three fifos contained in the compressor/decompressor block. all fifos operate identically from both a hardware and firmware standpoint. the fifo structure is illustrated in figure 14-2. the fifos consist of a quad halfword fifo structure and a single halfword holding register. the quad fifo structure is emptied and filled by either dma or cpu operations. the holding register is emptied and filled by the compressor/decompressor logic. all locations within the fifo can also be arbitrarily read and written by firmware. this allows firmware to save the entire fifo state and restore it at a later point in time, thereby permitting an unlimited number of data streams to be concurrently processed. mux t4 (mh, mr), t6(mmr) code or decode line cpu data dma ch 10 data dma ch 7 dma ch 6 t4 bi-level resolution conversion dma ch 8 t4/t6 compression/decompression t4data fifo3 current line buffer data (uncoded data) reference line buffer data (uncoded data) figure 14-1. data flow for compression/decompression
MFC2000 multifunctional peripheral controller 2000 hardware description 14-2 conexant 100723a system data bus holding register quad halfword 0 quad halfword 1 quad halfword 2 quad halfword 3 fifo control local data bus figure 14-2. compressor/decompressor fifo structure 14.2 register description address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default t4 configuration (t4config) $01ff8171 (not used) (not used) (not used) (not used) (not used) disable hardware dma ch10 disable hardware dma ch6 disable hardware dma ch7 rst. value xxxxx000b read value: 00000000b address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default t4 configuration (t4config) $01ff8170 (not used) enable smart eol operation enable non- inverted flush (zero fill) compressed data src./dest. 00=t4data0 01=t4data1 10=t4data2 11=t4data3 enable decompressi on t4 coding/decoding mode 00=mh 01=mr 1-dimensional 10-mr 2-dimensional 11=mmr rst. value x0000000b read value: 00000000b bit 15-11: not used bit 10: disable coded hardware dma. setting this bit to 1 disables hardware dma accesses to the coded data fifos (dma ch10). clearing this bit allows hardware dma to the coded data fifos. this bit should be set when firmware dma is to be carried out to the coded data fifo. bit 9: disable uncoded hardware dma. setting this bit to 1 disables hardware dma accesses to the uncoded data fifo (dma ch6). clearing this bit allows hardware dma to the uncoded data fifo. this bit should be set when firmware dma is to be carried out to the uncoded data fifo.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 14-3 bit 8: disable reference hardware dma. setting this bit to 1 disables hardware dma accesses to the reference data fifo (dma ch7). clearing this bit allows hardware dma to the reference data fifo. this bit should be set when firmware dma is to be carried out to the reference data fifo. bit 7: not used bit 6: enable smart eol operation. setting the smart eol operation bit causes the posting of an eol in the t4 status register to be delayed until the selected t4data fifo has transferred all of its data. clearing the bit causes eol to be set as soon as the eol has been processed, regardless of the condition of the fifo. bit 5: enable non-inverted flush. setting the non-inverted flush bit causes the flush operation to use zero as fill bits rather than the inverted value of the last cw bit. inverted fill allows the user to determine the number of fill bits added to halfword align the last cw. bit 4-3: compressed data source/destination. 00=t4data0 (default) 01=t4data1 10=t4data2 11=t4data3 warning: no distinction is made between fifo accesses by either the dma channel or the cpu. this means it is possible for both sources to modify the fifo contents, resulting in unpredictable operation of the compressor/decompressor. firmware must ensure that the cpu does not modify the fifo contents without first disabling the dma channel. bit 2: enable decompression bits 1-0: t4 coding/decoding mode 00=mh01=mr 1-d 10=mr 2-d11=mmr when mmr compression is selected, 2-d coding will occur (similar to mr 2-d), however, the last cw in the line will not be halfword aligned by adding fill bits. code words from the next compressed line will be concatenated to whatever is already in the selected t4data fifo. mmr decompression is similar to mr 2-d decoding, except that the end-of-line condition is based on the number of decoded bits rather than an eol code word.
MFC2000 multifunctional peripheral controller 2000 hardware description 14-4 conexant 100723a address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default t4 control (t4control) $01ff8173 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value: 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default t4 control (t4control) $01ff8172 reset t4 block (w) terminating code error enable bi- level resolution conversion decode output enable vertical or enable (decompress mode only) reset/halt coding or decoding start coding or decoding flush cw (completes byte) rst. value x0000000b read value 00h bit 15-8: not used bit 7: writing a 1 to this bit causes the t4 logic to be reset, including all internal state machines and fifos. this bit is useful when switching between compression and decompression modes. bit 6: a terminating code error is indicated when a run length = 0 code is expected but not received at the end of a line, and the terminating code error also sets the line error bit bit 5: enable bi-level resolution conversion. bi-level resolution conversion is only valid in decompression mode. when this bit is set, horizontal resolution conversion will be performed on the decoder output. both the unconverted line and the converted line will be output to the line buffer. the converted line will be written to the line buffer via dma channel 8. bit 4: decode output enable. decode output enable allows decoded data to be output to the line buffers. this bit should not be set in mh or mr decoding until the first eol has been found. the decoder output should also be disabled after an error line until the next eol is found. this bit should always be set for the mmr decoder. bit 3: vertical or enable. the vertical or bit is only valid in decompression mode when the bi- level resolution conversion bit in the t4config register is also set. when the vertical or bit is set, the resolution converted decoded output data is ored with the corresponding byte from the previous line before storing. bit 2: reset or halt the coding or decoding. setting the reset/halt bit immediately halts coding or decoding of a line, resets all the t4 status bits, and clears the active t4data fifo. all other bits in this register are ignored if the reset/halt bit is set. when coding or decoding is in progress, writing to any bit in this register except reset/halt is ignored. bit 1: start coding or decoding. the start bit begins the coding or decoding of the line according to the configuration selected per the t4config register.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 14-5 bit 0: flush the code word. the flush cw bit is only valid during mmr compression mode. writes to this bit are ignored when coding/decoding is in progress, or when decompression is selected. when the flush cw bit is set at the end of coding a line, it causes any data in the active t4data fifo to be filled in order to make a complete halfword which can then be read by the cpu or dma controller. the fill bits are the opposite value of the last cw bit, unless the non-inverted flush bit in the t4config register is set. in this case, the data is flushed with zeros. one halfword is always output when the flush bit is set even if the last cw is already halfword aligned. address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default t4 status (t4status) $01ff8174 (r) t4 datax dma page boundary t4 datax fifo dma acknowledge t4 datax fifo dma request write t4datax fifo ready read t4datax fifo ready write uncoded fifo ready read uncoded fifo ready write reference fifo ready rst. value 00h read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default t4 status (t4status) $01ff8175 (r) eol condition tag bit non- consecutive eol/ mmreol line error line error type all white line rst. value 00h read value 00h bit 15: this a copy of the hardware signal from the dma channel indicating when the dma block size has been reached and is used by the fifo to prevent its dma request from being asserted if smart eol operation has been enabled via the t4 configuration register. bit 14: this is a copy of the hardware signal from the dma channel indicating a dma transfer is in progress. bit 13: this is a copy of the hardware signal to the dma channel indicating the desire to initiate a dma transfer. bit 12: the wrt4datafifordy bit is set during decompression mode when the active t4data fifo is not full and is cleared when the fifo is full. bit 11: the rdt4datafifordy bit is set when compressed data is available in the active t4data fifo. this bit is cleared when there is no data available. bit 10: the wruncodedfifordy bit is set during compression mode when the uncoded line fifo is not full and is cleared when the fifo is full. bit 9: the rduncodedfifordy bit is set when uncompressed data is available in the uncoded line fifo. this bit is cleared when there is no data available. bit 8: the wrreffifordy bit is set during either mr/mmr compression or decompression mode when the reference line fifo is not full and is cleared when the fifo is full.
MFC2000 multifunctional peripheral controller 2000 hardware description 14-6 conexant 100723a bit 7: end of line conditions. for coding, the end-of-line condition occurs when all data in the line has been compressed and the last codeword has been written to the t4data fifo. for decoding, the end-of-line condition occurs when the decoding of a line is complete, and all decoded data has been written to the line buffer. for mh and mr modes, decoding is complete when the eol codeword (and tag bit if in mr mode) have been decoded. for mmr mode, decoding is complete when the number of bytes specified by the t4bytes register have been decoded. bit 6: the tag bit is only valid when the end-of-line condition bit is also set. bit 5: the nonconsecutiveeol/mmreol is only valid when the end-of-line condition bit is also set. bit 4: line error. line errors apply to the decoding mode only. if a line error occurs while decoding a line, the t.4 hardware will set the lineerror bit. decoding will continue until an eol code is found (mh and mr modes only), but data decoded following the error will not be output to the line buffer.. the type of line error can be determined by examing the line error type bit field. bit 3-1: line error type. when a line error occurs, the type of line error is placed in this bit field. the following line errors are detected by the t.4 hardware: lineerror code: error: description: 000b no error 001b rtc (return to control) error fill bits occurred between consecutive eol codewords. 010b terminating code error codewords for white or black run lengths equal to zero which occur at the end of a line are missing. when this error occurs the tc error bit (t4status register) is set as well as the normal error bit; this is to allow the user to ignore these errors if desired. 011b reserved 100b line too short eol code found before the number of bytes specified in the t4bytes register have been decoded. 101b line too long the number of data bytes decoded before the eol code is received exceeds the line length specified in the t4bytes register. 110b code word error an invalid code word was decoded. 111b reserved bit 0: indicate the decoded line is all white when this bit is set. this bit is reset when the decoding of a line is started. notes: 1. an irq is generated whenever any of the shaded bits shown in the t4 status register (bits 4, 7?9) and their associated bits in the t4intmask register are both set. 2. bits 0?6, and 9 only apply to decompression mode. 3. bits 0?7 are cleared at the start of a new line.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 14-7 address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default t4 line length (t4halfwords) $01ff8179 (not used) (not used) (not used) (not used) (not used) (not used) line length bits 9-8 rst. value xxxxxx00b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default t4 line length (t4halfwords) $01ff8178 line length bits 7-0 rst. value 00h read value 00h bit 15-10: not used bit 9-0: line length the t4 line length register defines the number of bytes in the line to be coded or decoded. line length values from 001h through 3ffh correspond to 1 through 1023 halfwords of data. address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default t4 interrupt mask (t4intmask) $01ff8177 (not used) (not used) (not used) enable wr t4data fifo rdy enable rd t4data fifo rdy enable wr uncoded fifo rdy enable rd uncoded fifo rdy enable wr ref fifo rdy rst. value xxx00000b read value: 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default t4 interrupt mask (t4intmask) $01ff8176 enable end of line (not used) (not used) enable line error (not used) (not used) (not used) (not used) rst. value 0xx0xxxxb read value 00h bit 15-13: not used bit 12: wrt4datafifordy enable interrupt bit 11: rdt4datafifordy enable interrupt bit 10: wruncodedfifordy enable interrupt bit 9: rduncodedfifordy enable interrupt bit 8: wrreffifordy enable interrupt bit 7: end of line enable interrupt. bit 6-5: not used bit 4: line error enable interrupt. bit 3-0: not used the four interrupt enable bits correspond to bits in the t4 status register. the position of each interrupt enable bit is in the same place as its corresponding bit in the t4 status register (bit 7 ? end of line enable interrupt corresponds to bit 7 ? eol condition).
MFC2000 multifunctional peripheral controller 2000 hardware description 14-8 conexant 100723a address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default t4 fifo bits remaining register (t4fifobitrem) $01ff817b (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value: 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default t4 fifo bits remaining register (t4fifobitrem) $01ff817a (not used) (not used) (not used) (not used) bits remaining rst. value xxxx0000b read value x0000000b bit 15-4: not used bit 3-0: number of bits remaining in fifo (holding register), with values ranging from 0 to 15. the interpretation of bits remaining depends on the direction of data flow. if the compressor/decompressor is emptying the fifo, bit remaining is the number of that contain data that have yet to be processed. if the compressor/decompressor is filling the fifo, bits remaining is the number of bits that are empty. t.4 data fifo halfword[3:0] for the coded data to/from the external memory (for dma channel 10): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 data fifo (t4data1fifox) data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value xxh read value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 data fifo (t4data1fifox) data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value xxh read value xxh ? address assignment for t.4 data fifo halfword[3:0] fifo halfword the register name address fifo halfword 3 t4datafifo3 01ff8117-16 fifo halfword 2 t4datafifo2 01ff8115-14 fifo halfword 1 t4datafifo1 01ff8113-12 fifo halfword 0 t4datafifo0 01ff8111-10
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 14-9 t.4 ref. line data fifo halfword[3:0] for the uncoded data to/from the external memory (for dma channel 7): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 reference line data fifo (t4refdatafifox) data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value xxh read value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 reference line data fifo (t4refdatafifox) data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value xxh read value xxh ? address assignment for t.4 ref. line data fifo halfword[3:0] fifo halfword the register name address fifo halfword 3 t4refdatafifo3 01ff8157-56 fifo halfword 2 t4refdatafifo2 01ff8155-54 fifo halfword 1 t4refdatafifo1 01ff8153-52 fifo halfword 0 t4refdatafifo0 01ff8151-50 t.4 current line data fifo halfword[3:0] for the uncoded data to/from the external memory (for dma channel 6): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 current line data fifo (t4curdatafifox) data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value xxh read value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 reference line data fifo (t4curdatafifox) data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value xxh read value xxh ? address assignment for t.4 current line data fifo halfword[3:0] fifo halfword the register name address fifo halfword 3 t4curdatafifo3 01ff8167-66 fifo halfword 2 t4curdatafifo2 01ff8165-64 fifo halfword 1 t4curdatafifo1 01ff8163-62 fifo halfword 0 t4curdatafifo0 01ff8161-60
MFC2000 multifunctional peripheral controller 2000 hardware description 14-10 conexant 100723a t.4 data fifo holding register for the coded data to/from the external memory (for dma channel 10): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 data fifo holding register (t4data1hold) $01ff8119 data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value xxh read value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 data fifo holding register (t4data1hold) $01ff8118 data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value xxh read value xxh t.4 ref. line data fifo holding register for the uncoded data to/from the external memory (for dma channel 7): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 ref. line data fifo holding register (t4refdatahold) $01ff8159 data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value xxh read value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 ref. line data fifo holding register (t4refdatahold) $01ff8158 data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value xxh read value xxh t.4 current line data fifo holding register for the uncoded data to/from the external memory (for dma channel 6): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 current line data fifo holding register (t4curdatahold) $01ff8169 data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value xxh read value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 current line data fifo holding register (t4curdatahold) $01ff8168 data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value xxh read value xxh
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 14-11 t.4 data fifo control register for the coded data to/from the external memory (for dma channel 10): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 data fifo control register (t4data1fifoctrl) $01ff811b fifo enabled (r) data request (r) fifo ready (r) fifo dma threshold fifo output pointer rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 data fifo control register (t4data1fifoctrl) $01ff811a (not used) holding register full (not used) fifo data quantity fifo input pointer rst value x0x00000b read value 00h bit 15 this bit indicates that the fifo is active and capable of generating dma requests. bit 14 this bit is essentially a copy of the dma request output signal and indicates that the fifo wishes to transfer data. bit 13 this bit indicates that the fifo can accept data transfers to/from the local logic. this bit is low when the data direction is into the local logic and the fifo is empty or when the data direction is out of the local logic and the fifo is full. bit 12-10 this bit field indicates at which point the fifo should issue a dma request. it is compared with the fifo data quantity bit field to determine when this should occur. legal values are from 0 to 4. values greater than 4 are treated as 4. bit 9-8 this bit field indicates which byte of the fifo quad halfword structure is the next to be used as output data. bit 6 this bit indicates that there is a full word in the holding register bit 4-2 this bit field indicates the number of quad halfwords that contain data. valid values are from 0 to 4. bit 1-0 this bit field indicates which byte of the fifo quad halfword structure is the next to receive input data. note: it is strongly recommended that the fifo be disabled before firmware writes to the fifo control register. the fifo control register contains data that is essential to the fifo?s operation. if this data is changed while the fifo is operating, unpredictable operation will result.
MFC2000 multifunctional peripheral controller 2000 hardware description 14-12 conexant 100723a t.4 ref. line data fifo control register for the uncoded data to/from the external memory (for dma channel 7): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 ref. line data fifo control register (t4refdatafifoctrl) $01ff815b fifo enabled (r) data request (r) fifo ready (r) fifo dma threshold fifo output pointer rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 ref. line data fifo control register (t4refdatafifoctrl) $01ff815a (not used) holding register full (not used) fifo data quantity fifo input pointer rst value x0x00000b read value 00h t.4 current line data fifo control register for the uncoded data to/from the external memory (for dma channel 6): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 current line data fifo control register (t4curdatafifoctrl) $01ff816b fifo enabled (r) data request (r) fifo ready (r) fifo dma threshold fifo output pointer rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 current line data fifo control register (t4curdatafifoctrl) $01ff816a (not used) holding register full (not used) fifo data quantity fifo input pointer rst value x0x00000b read value 00h t.4 data fifo data port for the coded data to/from the external memory: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 data fifo data port (t4data1port) $01ff811d data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value xxh read value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 data fifo data port (t4data1port) $01ff811c data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value xxh read value xxh
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 14-13 address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default t4 data fifo data port transfer (t4data1porttfr) $01ff814f (dw) (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value: xxh address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default t4 data fifo data port transfer (t4data1porttfr) $01ff814e (dw) (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value xxh bit 15-0: not used. writing any value to this register causes the data in fifo to push or pop data through the fifo data port and the fifo quad halfword 1-4 registers. the fifo operation depends on the direction of data flow. if the compressor/decompressor is emptying the fifo, data is transferred from the fifo data port register to the fifo quad halfword 1 register, simultaneously with data transfer from quad halfword 1 to quad halfword 2, quad halfword 2 to quad halfword 3, and quad halfword 3 to quad halfword 4, with the original data of quad halfword 4 being lost. if the compressor/decompressor is filling the fifo, data is transferred from the fifo quad halfword 1 register to the fifo data port register, simultaneously with data transfer from quad halfword 2 to quad halfword 1, quad halfword 3 to quad halfword 2, and quad halfword 4 to quad halfword 3, with the contents of quad halfword 4 becoming indeterminate. t.4 ref. line data fifo data port for the uncoded data to/from the external memory: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 ref. line data fifo data port (t4refdataport) $01ff815d data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value xxh read value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 ref. line data fifo data port (t4refdataport) $01ff815c data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value xxh read value xxh address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default t4 ref. line data fifo data port transfer (t4refdataporttfr) $01ff815f (dw) (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value: xxh address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default t4 ref. line data fifo data port transfer (t4refdataportfrt) $01ff815e (dw) (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value xxh
MFC2000 multifunctional peripheral controller 2000 hardware description 14-14 conexant 100723a bit 15-0: not used writing any value to this register causes the data in fifo to push or pop data through the fifo data port and the fifo quad halfword 1-4 registers. the fifo operation depends on the direction of data flow. if the compressor/decompressor is emptying the fifo, data is transferred from the fifo data port register to the fifo quad halfword 1 register, simultaneously with data transfer from quad halfword 1 to quad halfword 2, quad halfword 2 to quad halfword 3, and quad halfword 3 to quad halfword 4, with the original data of quad halfword 4 being lost. if the compressor/decompressor is filling the fifo, data is transferred from the fifo quad halfword 1 register to the fifo data port register, simultaneously with data transfer from quad halfword 2 to quad halfword 1, quad halfword 3 to quad halfword 2, and quad halfword 4 to quad halfword 3, with the contents of quad halfword 4 becoming indeterminate. t.4 current line data fifo data port for the uncoded data to/from the external memory: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: t.4 current line data fifo data port (t4curdataport) $01ff816d data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value xxh read value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: t.4 current line data fifo data port (t4curdataport) $01ff816c data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value xxh read value xxh address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default t4 current line data fifo data port transfer (t4curdataporttfr) $01ff816f (dw) (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value: xxh address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default t4 current line data fifo data port transfer (t4curdataporttfr) $01ff816e (dw) (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value xxh bit 15-0: not used writing any value to this register causes the data in fifo to push or pop data through the fifo data port and the fifo quad halfword 1-4 registers. the fifo operation depends on the direction of data flow. if the compressor/decompressor is emptying the fifo, data is transferred from the fifo data port register to the fifo quad halfword 1 register, simultaneously with data transfer from quad halfword 1 to quad halfword 2, quad halfword 2 to quad halfword 3, and quad halfword 3 to quad halfword 4, with the original data of quad halfword 4 being lost. if the compressor/decompressor is filling the fifo, data is transferred from the fifo quad halfword 1 register to the fifo data port register, simultaneously with data transfer from quad halfword 2 to quad halfword 1, quad halfword 3 to quad halfword 2, and quad halfword 4 to quad halfword 3, with the contents of quad halfword 4 becoming indeterminate.
multifunctional peripheral controller 2000 MFC2000 100723a conexant 15-1 15. synchronous/asynchronous serial interface (sasif) 15.1 functional description the sasif is a synchronous/asynchronous receiver/transmitter which performs serial-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion of data for transmission to a peripheral device. the interface consists of serial transmit data (sastxd), serial receive data (sasrxd), and a serial clock (sassclk) signals. figure 15-1 is a block diagram of the sasif. the sasif includes a programmable baud rate generator for asynchronous and synchronous operations. four interrupts can be generated for the arm. these are transmit shift register empty, transmit buffer register empty, or receive buffer register full, and receive fifo timeout. these interrupts can each be uniquely enabled or disabled. the sasif can also be set to fifo mode. in this mode, the arm will be relieved of excessive interrupt handling and will allow for an overall faster transmit and receive speed. a fifo mode can be enabled for either the receive portion or the transmit portion of the sasif. when the transmit fifo is enabled, a 16-byte fifo will be used to hold up to 16 bytes of data to be transmitted. the transmit buffer empty interrupt will only be generated if the transmit fifo has no new data to transmit (it is empty). when the receive fifo is enabled, a 16-byte fifo will be used to store up to 16 bytes of data which are received from the receive shift register. the receive buffer full interrupt will only be generated if the receive fifo has no room left for incoming data (it is full). the receive fifo also includes a timeout function. if the receive fifo is not full, but the last newly received byte was longer than four byte times ago (based on the programmed baud rate), then a timeout interrupt will be generated. a ?byte time? is the time in which it takes to receive one byte of data. the receive and transmit data is double buffered to provide more time for the arm to process receive data. the data shifting order, msb to lsb or lsb to msb, and the sasclk polarity are programmable. the synchronous communication mode enables the arm to transmit and receive data synchronous referencing to the serial clock. the arm can read the status of the sasif at any time during operation. status includes irq source (sastxd or sasrxd) and operation mode (synchronous or asynchronous). during the input/output mode the sastxd, sasrxd, and sassclk values can also be read or written by the arm. the contents of each byte within the transmit and receive fifo can be read any time during operation, as well as the input and output pointers to both fifos. following is the feature summary of the serial interface: ? full duplex, three wire system: sassclk (serial clock), sastxd (transmit data), sasrxd (receive data) ? independent transmit data shift register and receive data shift register ? double buffered receive and transmit data register ? programmable 7 or 8 data bit asynchronous serial-interface with a start bit, a stop bit and no parity ? 8 data bit synchronous serial-interface with programmable data shifting order ? programmable baud rate generator supports up to 14400 baud asynchronous transmit and receive (when in fifo mode is not on), and up to 2 iclk synchronous transmit and receive ? supports up to 115.2 kbaud asynchronous transmit and receive when in fifo mode ? single interrupt generation for transmit data shift register empty, transmit data buffer register empty, receive data buffer register full, and receive fifo timeout ? in the fifo mode, transmitter and receiver are each buffered with 16 byte fifo?s to reduce the number of interrupts to the arm. ? maximum 1% sastxd async transmit baud rate error ? maximum 2.5% sasrxd async receive baud rate allowable error
MFC2000 multifunctional peripheral controller 2000 hardware description 15-2 conexant 100723a sclkctrllo sclkctrlhi clockgen txrxcontrol iocontrol sasirq control sascommand reg txbuffer reg (sasdata) txshift reg sastxd sassclk cpu bus sasrxd rxbuffer reg (sasdata) rxshift reg sasirqctrl irqsasif figure 15-1. sasif block diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 15-3 15.2 register description address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: sascmd 01ff80f1 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: sascmd 01ff80f0 (not used) txfifoenb rxfifoenb l2msb sassclkpo l datalen sasmode rst. value x0000000b read value 00h register description : sasif command register bit 15-7: not used bit 6: txfifoenb ? read/write bit. this bit controls whether or not the 16-byte transmit fifo is to be used. when the txfifoenb is cleared (default), the transmit fifo will not be used and an interrupt will be generated each time a byte is sent. if txfifoenb is set, the transmit fifo will be used and an interrupt will be generated only when the fifo is completely emptied. this should only be written to during setup and not after the sasif has started sending or receiving data, as data loss could occur. bit 5: rxfifoenb ? read/write bit. this bit controls whether or not the 16-byte receive fifo is to be used. when the rxfifoenb is cleared (default), the receive fifo will not be used and an interrupt will be generated for each byte received. if rxfifoenb is set, then the receive fifo will be used and an interrupt will only be generated if the fifo is full or a receive fifo timeout occurs. this should only be written to during setup and not after the sasif has started sending or receiving data, as data loss could occur. bit 4: l2msb ? read/write bit. this bit controls the shifting order of the transmit and receive registers. when the l2msb bit is cleared (default) and the sasif is set to the asyncmode or syncmode, the transmit and receive shift register will shift from the msb to the lsb. when the l2msb bit is set, the transmit and receive register will shift from the lsb to msb. bit 3: sassclkpol ? read/write bit. this bit controls the polarity of the sassclk pin for the sync mode. when the sassclkpol bit is cleared (default) and the sasif is set to asyncmode or syncmode, the sassclk polarity will be non-inverted, which will enable the external logic to clock the sastxd pin on the rising edge of the sassclk pin. when the sassclkpol bit is set and the sasif is set to asyncmode or syncmode, the sassclk polarity will be inverted, which will enable the external logic to clock the sastxd pin on the falling edge of the sassclk pin. bit 2: datalen ? read/write bit. this bit controls the number of bit for asyncmode transmit. this bit is not effective for the syncmode. when the datalen is cleared (default) and the sasif is set to the asyncmode, the txbuffer register bit 7 will be the msb and bit 0 will be the lsb for asynchronous transmit. the transmit shifting order is controlled by the l2msb bit. when the datalen is set and the sasif is set to the asyncmode, the txbuffer register bit 6 will be the msb and bit 0 will be the lsb for asynchronous transmit.
MFC2000 multifunctional peripheral controller 2000 hardware description 15-4 conexant 100723a bit1-0: sasmode ? read/write bits. these two bits control the sasif operation modes. 00: asyncmode (default) 01: syncmode 10 & 11: reserved note: the txfifo enable and the rxfifo enable should either be set or cleared once in the setup of the sasif device. enabling or disabling the fifos once the mfc is up and running could have unpredicted results if data is being received or sent by the shift registers. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: sasrxdata 01ff80f3 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: sasrxdata 01ff80f2 sasrx data(7) sasrx data(6) sasrx data(5) sasrx data(4) sasrx data(3) sasrx data(2) sasrx data(1) sasrx data(0) rst. value 00h read value 00h register description: sasif rx data buffer register note: this is the receive buffer data register. reading from this register will return the data in the rxbuffer (for fifo disabled) or the oldest valid received data (for fifo enabled). however, after a read, a write must be done to this register in order to let the sasif know that data has been read. this was done to help with emulation testing. writing to the sasdata register will clear the rxbuffull or rxfifothresh status bits. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: sastxdata 01ff80fb (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: sastxdata 01ff80fa sastx data(7) sastx data(6) sastx data(5) sastx data(4) sastx data(3) sastx data(2) sastx data(1) sastx data(0) rst. value 00h read value 00h register description: sasif tx data buffer register (write only) note: this is the transmit buffer data register. it is a write only register. writing to this register placed data into the transmit buffer register (or the transmit fifo if txfifo is enabled). writing to the sastxdata register will clear the txbufempty or txfifothresh status bits.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 15-5 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: sasfifoptr 01ff80f7 tx input pointer tx output pointer rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: sasfifoptr 01ff80f6 rx input pointer rx output pointer rst. value 00h read value 00h register description: sasif fifo pointer register bit 15-12: transmit fifo input pointer (read only bit) bit 11-8: transmit fifo output pointer (read only bit) bit 7-4: receiver fifo input pointer (read only bit) bit 3-0: receiver fifo output pointer (read only bit) address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: sasfifoqty 01ff80fd (not used) tx fifo quantity txfifothreshval rst. value x0000011b read value 00000011b address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: sasfifoqty 01ff80fc (not used) rx fifo quantity rxfifothreshval rst. value x0000011b read value 00000011h register description : sasfifoqty register bit 15: not used bit 14-10: txfifoqty (transmit fifo quantity) ? read only bits. these five bits hold the value of the amount of bytes stored within the transmit fifo. as data is written to or removed from the txfifo, the quantity will be adjusted accordingly. bit 9-8: txfifothreshval (transmit fifo threshhold value) ? read/write bits. depending on how these two bits are set, will affect when the transmit fifo considers itself empty enough to cause an interrupt. bit value # of bytes left in txfifo which should cause interrupt ?00? 12 ?01? 8 ?10? 4 ?11? 2 bit 7: not used
MFC2000 multifunctional peripheral controller 2000 hardware description 15-6 conexant 100723a bit 6-2: rxfifoqty (receive fifo quantity) ? read only bits. these five bits hold the value of the amount of bytes stored within the receive fifo. as data is written to or removed from the rxfifo, the quantity will be adjusted accordingly. bit 1-0: rxfifothreshval (receive fifo threshhold value) ? read/write bits. depending on how these two bits are set, will affect when the receive fifo considers itself full enough to cause an interrupt. bit value # of bytes filled in rxfifo which should cause interrupt ?00? 4 ?01? 8 ?10? 12 ?11? 14 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: sasirqsts 01ff80f9 (not used) (not used) (not used) rxfifo overrun (read only) txfifofull (read only) txfifoempty (read only) rxfifofull (read only) rxfifoempt y (read only) rst. value xxh read value 05h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: sasirqsts 01ff80f8 rxtimeout elapsed (read only) rxtimeout enb txbufempty or txfifothres h (read only) txshfempty (read only) rxbuffull or rxfifothres h (read only) txbufirqenb txshfirqenb rxbufirqen b rst. value x0xxx000b read value 30h register description : sersasirqctrl register bit 15-13: not used bit 12: rxfifooverrun(receive fifo data loss) ? read only bit. this bit goes high when the receive fifo is completely full, but an extra byte has just been received by the rxshiftreg. this will not cause an interrupt, but the rxfifothresh should already have done so. bit 11: txfifofull(transmit fifo full) ? read only bit. this bit goes high when the transmit fifo is completely full. data cannot be written to the transmit fifo after this point. this will not cause an interrupt. this is helpful when trying to figure out if more bytes can be written to the transmit fifo. bit 10: txfifoempty(transmit fifo empty) ? read only bit. this bit goes high when the transmit fifo is completely empty. this will not cause an interrupt, but the txfifothresh should have already done so.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 15-7 bit 9: rxfifofull(receive fifo full) ? read only bit. this bit goes high when the receive fifo is completely full. new received data received from the rxshiftreg will be thrown away. this will not cause an interrupt, but the rxfifothresh should have already done so. bit 8: rxfifoempty(receive fifo empty) ? read only bit. this bit goes high when the receive fifo is completely empty. this will not cause an interrupt. this can be helpful in trying to figure out if more data can be read from the receive fifo. bit 7: rxtimoutelapsed (receive fifo timeout occurred) ? read only bit. the rxtimoutelapsed shows the status of the timeout function of the receive fifo. when the rxtimoutelapsed is set, the timer has timed out which means that the fifo has not received any new data for too long of a time, but the fifo is not full. when this bit is cleared, the receive fifo is running properly. this will cause an interrupt in conjunction with rxtimeoutenb bit 6: rxtimeoutenb (receive timeout interrupt enable) ? read/write bit. when the rxtimerenb is cleared (default), the rxtimeoutirq signal will be disabled. when the rxtimerenb bit is set, the rxtimeoutirq will be enabled. bit 5: txbufempty/txfifothresh (transmit data buffer register empty or transmit fifo threshhold met) ? read only bit. the txbufempty bit shows the status of the transmit buffer register when txfifo is disabled. the transmit buffer register is empty when this bit is set. the transmit buffer register is when this bit is cleared. when txfifo is enabled, the transmit fifo has met its threshhold limit when this bit is set, and is not yet emptied to its threshhold when this bit is cleared. this bit will cause an interrupt in conjunction with txbufirqenb. bit 4: txshfempty (transmit shift data register empty) ? read only bit. the txshfempty bit shows the status of the transmit shift register. the transmit shift register is empty when this bit is set. the transmit shift register is full when this bit is cleared. bit 3: rxbuffull/rxfifothresh (receive buffer register full or receive fifo threshhold met) ? read only bit. the rxbuffull bit show the status of the receive buffer register (when rxfifo is disabled). the receive buffer register is empty when this bit is cleared. the receive buffer register is when this bit is set. when rxfifo is enabled, the receive fifo has met its threshhold when this bit is set, and is not yet filled to its threshhold limit when this bit is cleared. this bit will cause an interrupt in conjunction with rxbufirqenb.
MFC2000 multifunctional peripheral controller 2000 hardware description 15-8 conexant 100723a bit 2: txbufirqenb (transmit buffer irq enable) ? read/write bit. when the txbufirqenb bit is cleared (default), the txbufirq signal is disabled. the txbufirq will be activated, when the txbufirqenb control bit and the txbufempty status bit are set. bit 1: txshfirqenb (transmit shift empty irq enable) ? read/write bit. when the txshfirqenb bit is cleared (default), the txshfirq signal will be disabled. the txshfirq will be activated, when the txshfirqenb control bit and the txshfempty status bit are set. bit 0: rxbufirq (receive buffer irq enable) ? read/write bit. when the rxbufirqenb bit is cleared (default), the rxbufirq signal will be disabled. the rxbufirq will be activated, when the rxbufirqenb control bit and the rxbuffull status bit are set. for monitoring the txbuffer, txshift, and rxbuffer register status, the sasif has four status bits. they are txbufempty, txshfempty, rxbuffull, and rxtimerelapsed status bits. following are the conditions when the status bits are set and cleared: txbufempty txshfempty rxbuffull 1 set when 1. the system resets, or 2. the last bit of the txshift register is sent to the sastxd pin 1. the system resets, or 2. the txbufempty status bit is set and the last bit of the txshift register is sent to the sastxd pin. 1. the stop bit is received by the sasrxd pin. cleared when 1. the cpu writes to the sasdata register, and 2. the txshfempty status bit is cleared. 1. the cpu writes to the sasdata register, and 2. the txbufempty status bit is set. 1. the system reset, or 2. the cpu reads the sasdata register. rxtimerelapsed set when when all of these are true for the time it would take to receive 4 bytes into the rx buffer. the rxfifo is not full, no start bit has been received, the sasrxdata register has not been read and written back to. cleared when 1. the system resets 2. the cpu writes to the sasrxdata register
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 15-9 for keeping track of the transmit and receive activities, the sasif has four separate interrupts -- the txbufirq, txshfirq, rxbufirq, and rxtimeoutirq. any of these interrupt activate will turn on the irqsasif. following are the conditions when they are set and cleared: txbufirq txshfirq rxbufirq 1 activated when 1. the txbufempty status bit is set, and 2. the txbufirqenb control bit is set. 1. the txshempty status bit is set, and 2. the txshfirqenb control bit is set, and 1. the rxbuffull status bit is set, and 2. the rxbufirqenb control bit is set. deactivated when 1. the txbufempty status bit is cleared, or 2. the txbufirqenb control bit is cleared. 1. the txshempty status bit is cleared, or 2. the txshfirqenb control bit is cleared. 1. the rxbuffull status bit is cleared, or 2. the rxbufirqenb control bit is cleared. rxtimeoutirq activated when 1. the rxtimerelapsed status bit is set, and 2. the rxtimerenb control bit is set. deactivated when 1. the rxtimerelapsed status bit is cleared, or 2. the rxtimerenb control bit is cleared. note: the rxbuffull status bit and the rxbufirq is valid in the asyncmode only. during the syncmode, data receive to the sasif is synchronous with the transmit data, therefore, the rxbuffull status bit and the rxbufirq signal is not used in the syncmode.
MFC2000 multifunctional peripheral controller 2000 hardware description 15-10 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: sasdiv 01ff80f5 sasrxd early 1 - early (not used) sassclk divisor upper bits (13-8) rst. value 0x000000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: sasdiv 01ff80f4 sassclk divisor lower bits (7-0) rst. value 00h read value 00h register description : this register controls bits of the sassclk divisor. bit 15: sasrxdearly (receive data early) ? read/write bit. if this bit is set to one (default = 0), the input data will be sampled 1/2 shift clock early from what is illustrated in figure 15-2. this is only for the sync mode. bit 14: not used bit 13-8: divhi (divisor high register) ? read/write bits. the divhi register is the higher bits (bit 13-8) of the sassclkdivisor register, which defines the sassclk frequency. bit 7-0: divlo (divisor low register) ? read/write bits. the divlo register is the lower bits (bit 7-0) of the sassclkdivisor register, which defines the sassclk frequency. writing the divlo register will cause the sasif logic to load the divhi and divlo to the internal counter. firmware can transmit data with the right speed immediately after the sassclk setup. the sassclk divisor register defines the sassclk frequency, which depends on the auxclk frequency (f tstclk ). the sassclkdivisor register has a fourteen bit divisor region. the sassclk frequency (f sclk )and divisor relationship is: for the sync mode, fint f divisor sclk auxclk = + ( * ) 22 for the async mode, fint f divisor sclk auxclk = + ( * ) 88
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 15-11 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: sastxfifon sasif tx fifo byte (2n + 1) rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: sastxfifon sasif tx fifo byte (2n) rst. value 00h read value 00h register description : sastxfifo register sastxfifo0 ? byte 0, 1 0x01ff8600-01 sastxfifo1 ? byte 2, 3 0x01ff8602-03 sastxfifo2 ? byte 4, 5 0x01ff8604-05 sastxfifo3 ? byte 6, 7 0x01ff8606-07 sastxfifo4 ? byte 8, 9 0x01ff8608-09 sastxfifo5 ? byte a, b 0x01ff860a-0b sastxfifo6 ? byte c, d 0x01ff860c-0d sastxfifo7 ? byte e, f 0x01ff860e-0f address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: sasrxfifon sasif rx fifo byte (2n + 1) rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: sasrxfifon sasif rx fifo byte (2n) rst. value 00h read value 00h register description : sasrxfifo register (read only register) sasrxfifo0 ? byte 0, 1 0x01ff8610-01 sasrxfifo1 ? byte 2, 3 0x01ff8612-03 sasrxfifo2 ? byte 4, 5 0x01ff8614-05 sasrxfifo3 ? byte 6, 7 0x01ff8616-07 sasrxfifo4 ? byte 8, 9 0x01ff8618-09 sasrxfifo5 ? byte a, b 0x01ff861a-0b sasrxfifo6 ? byte c, d 0x01ff861c-0d sasrxfifo7 ? byte e, f 0x01ff861e-0f
MFC2000 multifunctional peripheral controller 2000 hardware description 15-12 conexant 100723a 15.3 sasif timing 15.3.1 sassclk timing when sassclk is on (figure 15-2), the duty cycle of sassclk is always 50%. tserd tserd tserd tserd applies to sassclk, sastxd, and sasrxd when they are in output configuration auxclk sassclk sastxd sasrxd figure 15-2. sassclk timing diagram in figure 15-2, t serd is the auxclk to sassclk, sasrxd and sastxd delay. tserd applies to sassclk, sastxd, and sasrxd when they are in output configuration. the sassclk polarity is controlled by the sas command register sassclkpol bit. when the sassclkpol bit is cleared (default), the sastxd signal transition is on the sassclk falling edge. external logic can latch the sastxd signal on the sassclk rising edge. when the sassclkpol bit is set, the sastxd signal transition is on the rising edge of the sassclk. external logic can latch the sastxd signal on the sassclk falling edge. when configured in the syncmode, the sassclk will be active for eight cycles for each write to the empty sasdata register. continuous sassclk can be achieved by keeping the transmit buffer register full. when there is no data on the sastxd pin, the sassclk will stay in idle state, which is logic zero as the sassclkpol bit is clear and logic one as the sassclkpol bit is set. when configured in the asyncmode, the sassclk is a free running signal at the sassclkdivisor pre-defined clock rate. 15.3.2 synchronous mode timing when the sasif is configured to the syncmode, the sasif generates the sassclk signal to synchronize data transmit and receive. therefore, only the transmitter related status bit and irq signals are used, and the rxbuffull status bit and the rxbufirq signal are not used. 15.3.2.1 fifos disabled the txbufempty and txshfempty status bits are both set on system reset. when the fifos are disabled and both the txbuffer and txshift register are empty, writing to the sasdata register will clear the txshfempty status bit, and will fill the txshift register with the txbuffer register content. when the txbuffer is empty and the txshift register is non-empty, writing to the txbuffer register will clear the txbufempty status bit, and the txshift register is unaffected. when the txbuffer is full and the txshift register is empty, the txbuffer register value will be loaded into the txshift register. the txbufempty status bit will be set, and the txshfempty flag is unaffected.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 15-13 when both the txbuffer register and txshift register are empty, the txshfempty status bit will be set when the last bit of the data is shifted to the sastxd pin. 15.3.2.2 fifos enabled when fifos are enabled and the transmit fifo is completely empty and txshift register is empty, writing to the sasdata register will clear the txshfempty status bit, keep the txbufempty bit set and will fill the txshift register with the contents of the first fifo location written to. when the transmit fifo is completely empty and the txshift register is non-empty, writing to the transmit fifo (accomplished by writing sasdata) will clear the txbufempty status bit and the txshift register is unaffected (it will stay filled and the txshfenpty will stay cleared). when the transmit fifo is not empty and the txshift register is empty, the value of the oldest valid fifo location will be loaded into the txshift register. the txbufempty status bit will be set only if the last valid fifo location was just transferred to the txshift register. the txshfempty flag is unaffected. when the transmit fifo is completely empty and txshift register are empty, the txshfempty status bit will be set when the last bit of the data is shifted to the sastxd pin. 15.3.2.3 transmiting and sampling the sasrxd signal is sampled on the falling edge of the sassclk when the sassclkpol bit is cleared. sasrxd signal is sampled on the rising edge of the sassclk when the sassclkpol bit is set. if the sasrxdearly bit is set the sasrxd signal will be sampled 1/2 sassclk early. when the l2msb control bit is cleared, the msb to the lsb of the txshift register will be shifted to the sastxd pin, and the sasrxd signal will be shifted into the msb of the rxshift register. if the l2msb bit is set, the lsb to the msb of the txshift register will be shifted to the sastxd pin, and the sasrxd signal will be shift into the lsb of the rxshift register. the datalen bit is not used in the syncmode, eight data bits will be transmitted or received regardless of setting. msb lsb wr serdata d7 d7 d6 d5 d5 d4 d6 d3 d2 d4 d1 d3 d0 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb sassclk sastxd sasrxd sascs txbufem p t y txshfem p t y figure 15-3. synchronous mode timing 15.3.3 asynchronous mode transmitter timing once asyncmode is set, the transmitter logic will set sastxd to logic one and will stay in the transmitter idle state. after the arm writes to the sasdata register, sastxd will output the start bit (logic 0) on the next sassclk falling edge. starting from lsb of the txshift register (when l2msb is set), a total of 7 or 8 bits of data (depending on the datalen bit) will be sent. the bit next to the last data bit is the stop bit. similarly to the syncmode transmit timing, the txbufempty, txshfempty status bits, and the txbufirq, txshfirq has the same timing sequence. see figure 15-4.
MFC2000 multifunctional peripheral controller 2000 hardware description 15-14 conexant 100723a start lsb sto p wr serdata sastxd sassclk sascs txbufem p t y txshfem p t y figure 15-4. asynchronous transmitter timing the bit capture timing above is identical whether fifo mode is enabled or disabled. at the end of each transmitted byte, a new byte will be loaded from the txbuffer register when fifo mode is disabled, or from the oldest valid location with the fifo when fifo mode is enabled. following are the timing sequence for the interrupt control and byte loading control for both fifo enabled and fifo disabled modes: sascsn sastxd txfifoenb txload txbufempty txshfempty sas data wr sas data wr 123 15 16 1 bytes figure 15-5. asynchronous transmitter byte timing ? ? ? ? fifo mode enabled 15.3.3.1 asynchronous mode receiver timing once asyncmode is set, the receiver logic will look for a falling edge in the sasrxd signal and will stay in the receiver idle state. while sasrxd stays high, the receiver idles. when the start bit comes, the sasif edgedetector is triggered by the falling edge. until the next internal 8x baud rate clock arrives, the beginning of this character is defined. each bit has 8 8x baud rate clock pulses in it. data is sampled on the fourth baud8x clock from the receiving bit boundary. see figure 15-6. if the sampling value of the start bit is a logic 1, that start bit is regarded as a glitch or an invalid character, no rxbufirq will be generated. start bit sam p lin g lsb baud8x sasrxd figure 15-6. asynchronous receiver bit timing
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 15-15 after receiving the stop bit, when fifo mode is disabled, the serirq and the rxbuffull will both rise to a logic 1. rxbuffull and the serirq will be cleared by reading of the sasdata register. lsb sto p bit msb rd serdata start bit sasrxd sascs rxbuffull figure 15-7. asynchronous receiver byte timing ? fifo mode disabled when fifo-mode is enabled, after receiving the stop bit, the serirq and the rxbuffull will change to a logic 1 only if the receive fifo becomes full as a result of adding that last byte. both the interrupt and rxbuffull bit will be cleared when the sasdata register is read. sascsn sasrxd rxfifoenb rxload rxbuffull sas data rd 123 15 16 bytes figure 15-8. asynchronous receiver byte timing ? fifo mode enabled the last feature of the fifo mode is the timeout interrupt. in normal cases, the receive fifo only causes an interrupt when it is completely full. however, in the case where less than 16 bytes were received and no more bytes are being sent to the sasif, the timeout function tells the arm that no data has been received within the required amount of time, so a rxtimeoutirq occurs. the time required to cause this interrupt is based on the baud rate and is 4 times the ammount of time that it would take to send one byte of data into the rxshift register. so if no byte is transferred from the rxshift register to the receive fifo, nor is any bit shifted onto the rxshift register in that time, then the rxtimeoutirq will occur. here is an example of that: sascsn sasrxd rxfifoenb rxload txbaudend sas data rd rxtimerelapsed 123 4 32 beats without a rxload figure 15-9. asynchronous receiver fifo timeout ? ? ? ? fifo mode enabled
MFC2000 multifunctional peripheral controller 2000 hardware description 15-16 conexant 100723a 15.4 firmware operation 15.4.1 sasif syncmode operation syncmode setup 1. set the sassclkdivisor register for proper transmission rate. 2. set the l2msb bit for proper shifting order. 3. set the sassclkpol bit for proper sassclk polarity. 4. set the transmit fifo or receiver fifo to be enabled if lower system overhead or faster transfer rate is required. by default, the two fifo?s are disabled. 5. clear the txbufirqenb bit and/or the txshfirqenb bit if continuous transmitting is not required (lower cpu interrupt overhead and lower transfer rate), or set the txbufirqenb bit and the txshfirqenb bit if continuous transmission is needed (higher cpu interrupt overhead and higher transfer rate). 6. set the sasmode bit to select syncmode operations. note : steps 1 through 5 can be done in a setup-table load. data transmit and receive example ? fifo mode disabled case when the txbufirq and the txshfirq are enabled: 1. the arm writes first data to the sasdata register, and sets the txbufirqenb and the txshfirqenb bits. 2. the sasif loads the txbuffer register (sasdata register ) to the txshift register and clears the txshfempty status bit. 3. the sasif transmits, and receives bits 7 through bit 0 (if the l2msb bit is cleared) or bit 0 through bit 7 (if the l2msb bit is set). 4. by the end of the step 3 data shifting, the arm gets the txbufirq, which indicates that the txbuffer is ready for next transmit and the rxbuffer is full. 5. the arm reads the sasdata register for the rxbuffer register data, and clears the txbufirq by writing to the txbuffer register with the next data. if no more data, the arm clears the txbufirqenb bit. if only transmit is desired, the arm can ignore the data in the rxbuffer register. 6. if the txbufempty status bit is cleared at the end of the data shifting, the sasif will set the txbufempty bit and goto step 2. however, if the txbufempty bit is set, the sasif will set the txshfempty status bit and generates the txshfirq. 7. the arm gets the txshfirq, which indicates the end of all data shifting. if no data is wished to be sent or received, the arm can then clear the txshfirqenb bit. data transmit and receive example ? fifo mode (both fifo?s enabled) case when the txbufirq and the txshfirq are enabled: note : when using fifo mode in synchonous mode, both fifo?s must be enabled. this ensures that the rxfifo will contain the same number of bytes of data by the time the txbufirq occurs that were originally written to the txfifo. otherwise, since only tx interrupts are used, it will be impossible to grab the received data if no received fifo is used, and data will be lost if no txfifo is used when an rxfifo is used. 1. the arm writes first data to the sasdata register up to sixteen times in a row, filling up the txfifo as much as desired, and sets the txbufirqenb and the txshfirqenb bits.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 15-17 2. the sasif loads the oldest unused byte from the tx fifo to the txshift register and clears the txshfempty status bit. if this is the last byte held within the fifo, then a txbufirq and txbufempty status bit will be set, which indicates that the tx fifo is ready for next data to be loaded into it. 3. the sasif transmits, and receives bits 7 through bit 0 (if the l2msb bit is cleared) or bit 0 through bit 7 (if the l2msb bit is set). 4. by the end of the step 3 data shifting, if the tx fifo is empty then the arm will receive the txbufirq and txbuffempty status bit will be set, 5. if the txbufempty is cleared at the end of the data shifting (meaning there was leftover data in the txfifo), the sasif will set go back to step 2. however, if the txbufempty bit is set, the sasif will set the txshfempty status bit and generate the txshfirq. 6. the arm gets the txshfirq, which indicates the end of all data shifting. the arm reads the sasdata register as many times as it wrote to the sasdata register when filling up the tx fifo. after this, the next batch of data can be written to the tx fifo by writing up to sixteen times to sasdata. this clears the txbufempty bit and the txshfempty bit. if no more data needs to be sent, the arm clears the txbufirqenb and txshfirqenb bit. if only transmit is desired, the arm can ignore the data in the rx fifo. 15.4.2 sasif asyncmode operations asyncmode setup 1. set the sassclkdivisor register for proper transmission rate. 2. set the l2msb bit for proper shifting order. 3. set the sassclkpol bit for proper sassclk polarity. 4. set the datalen bit for proper data length. 5. choose whether to use the transmit fifo or the receive fifo. either, both, or neither can be used. 6. clear the txbufirqenb bit, the txshfirqenb, and the rxbufenb bit for lower cpu interrupt overhead and lower transfer rate, or set the txbufirqenb bit, the txshfirqenb, and the rxbufenb bit for higher cpu interrupt overhead and higher transfer rate. 7. set the sasmode bit to select asyncmode operations. note : steps 1 through 7 can be done in a setup-table load. asynchronous transmitter ? fifo mode disabled case when the txbufirq and the txshfirq are enabled: 1. the cpu writes data to the sasdata register (txbuffer register). this data is written at that time to the txbuffer register. 2. this data will automatically be transferred to the txshift register. 3. the sasif automatically transmits the start bit. 4. the sasif automatically clears the txshfempty status bit in the sercmd register or the txbufempty bit will be cleared if the txshfempty was already cleared. 5. the sasif automatically sends bits 0 through bit 6 (if 7 bit data is selected) or bit 7 (if 8 bit data is selected). 6. the sasif transmits the stop bit, sets the txbufempty bit only if the txbuffer register contains data (which will soon be transferred to the txshift register), or sets the txbufempty and the txshfempty bit if the txbuffer register is empty. if the txbufempty status bit is set and the txbufenb is set, the the arm will receive a txbufirq. if the txshfempty status bit is set and the txshfenb is set, the the arm will receive a txshfirq. 7. upon receiving these interrupts, the txshfenb or txbufenb can be cleared if no more data is wished to be sent, or a new byte of data can be written to the sasdata register. in the latter case, the txshfirq will be cleared and steps 2 through 6 will be repeated.
MFC2000 multifunctional peripheral controller 2000 hardware description 15-18 conexant 100723a asynchronous transmitter ? fifo mode disabled case when the txbufirq and the txshfirq are enabled: 1. the cpu writes up to 16 bytes in a row of data to the sasdata register (txbuffer register). this data will be written to the most current empty locations within the transmit fifo. 2. upon first writing to the transmit fifo, the data will automatically be transferred to the txshift register if the txshift register is currently empty. 3. the sasif automatically transmits the start bit. 4. the sasif automatically clears the txshfempty status bit in the sercmd register. 5. sasif automatically sends bits 0 through bit 6 (if 7 bit data is selected) or bit 7 (if 8 bit data is selected). 6. the sasif transmits the stop bit, sets the txbufempty bit only if the tx fifo is out of data (or is transfering its last byte to the txshift register), or sets the txbufempty and the txshfempty bit if the tx fifo is empty and has no data to give to the txshift register. if the txbufempty status bit is set and the txbufenb is set, the the arm will receive a txbufirq. if the txshfempty status bit is set and the txshfenb is set, the the arm will receive a txshfirq. 7. upon receiving these interrupts, the txshfenb or txbufenb can be cleared if no more data is wished to be sent, or steps 1 through 6 can be repeated. asynchronous receiver ? fifo mode disabled 1. the receiver is in idle state (sasrxd high) when the sasif receiver is waiting for falling a edge of the sasrxd (start bit) 2. the start bit activates the sasif receiver. 3. after receiving 7 or 8 data bits, sasif receiver looks for stop bit. 4. after receiving the stop bit, the sasif receiver will set the rxbuffull bit, and will generate a rxbufirq if the rxbufenb interrupt enable bit is set. 5. this serially received data is automatically transferred to the rxbuffer register. 6. an arm read of the sasdata register will retreive the data from the rx buffer register and will clear the rxbuffull status bit and the rxbufirq. asynchronous receiver ? fifo mode enabled 1. the receiver is in idle state (sasrxd high) when the sasif receiver is waiting for falling a edge of the sasrxd (start bit) 2. the start bit activates the sasif receiver. 3. after receiving 7 or 8 data bits, sasif receiver looks for stop bit. 4. after receiving the stop bit, the sasif receiver will set the rxbuffull bit, and will generate a rxbufirq if the rxbufenb interrupt enable bit is set. 5. this serially received data is automatically transferred to the current open location in the rx fifo. if the addition of this data makes the rx fifo full, then the rxbufirq will be activated (if the rxbufenb is set). when an interrupt is received, 16 bytes have been stored in the rx fifo. 6. an arm read of the rx fifo register (sasdata register) will clear the rxbuffull status bit and the rxbufirq, however it is advised that 16 consecutives reads take place at this time to fully empty out the rx fifo. 7. in the case that less than 16 bytes reside in the rx fifo but no more will be sent, if the rxtimerenb is set, then after the rx timer times out, then a rxtimeoutirq will be sent to the arm. note : each mention in the above descritions of rxtimeoutirq, rxbufirq, txshfempty, and txbufempty are actually all received by the arm as a single interrupt: serirq. in order to figure out which interrupt was received, the sasirqstatus register must be read, and then the appropriate action be taken.
multifunctional peripheral controller 2000 MFC2000 100723a conexant 16-1 16. usb interface 16.1 function description the usbif interface block interfaces to the pc, ipb bus and the dma block. it bridges print and scan data between the MFC2000 and the pc. it is compliant with usb protocol revision 1.1 and supports device remote- wakeup feature. there are six endpoints in the MFC2000, two control endpoints (including endpoint 0), two bulk in endpoints and two bulk out endpoints. the maxpacketsize for both the control endpoints are 8 byte and the maxpacketsize for the four bulk transfer pipes are 64 byte. endpoint 0 supports the get_descriptor and usb vendor/class commands. the usbif contains in-silicon usb device controller core, four uni-directional fifos and two bi-directional buffers. description of usb device controller core can be found in udc specification document. 16.2 register description address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep1fifo1 (r/w) $01ff8581 ep1 bulkin half word 1 reset. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep1fifo1 (r/w) $01ff8580 ep1 bulkin half word 1 reset. value 00h bits 15-0: endpoint 1 fifo quad half word 1 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep1fifo2 (r/w) $01ff8583 ep1 bulkin fifo 2 reset. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep1fifo2 (r/w) $01ff8582 ep1 bulkin half word 2 reset. value 00h read value 00h bits 15-0: endpoint 1 fifo quad half word 2 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep1fifo3 (r/w) $01ff8585 ep1 bulkin half word 3 reset. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep1fifo3 (r/w) $01ff8584 ep1 bulkin half word 3 reset. value 00h read value 00h bits 15-0: endpoint 1 fifo quad half word 3
MFC2000 multifunctional peripheral controller 2000 hardware description 16-2 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep1fifo4 (r/w) $01ff8587 ep1 bulkin half word 4 reset. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep1fifo4 (r/w) $01ff8586 ep1 bulkin half word 4 reset. value 00h read value 00h bits 15-0: endpoint 1 fifo quad half word 4 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep1hold (r/w) $01ff8589 ep1 bulkin holding register reset. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep1hold (r/w) $01ff8588 ep1 bulkin holding register reset. value 00h read value 00h bits 15-0: endpoint 1 fifo quad holding register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep1ctrl (r/w) $01ff858b fifo enabled (read only) data request (read only) fifo ready fifo dma threshold fifo output pointer rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep1ctrl (r/w) $01ff858a unused holding reg full byte present fifo data quantity fifo input pointer rst. value x0000000b read value 00h bit 15: this bit indicates that the fifo is active and capable of generating dma requests. this bit generally follows the setting of the lcl_enb input signal except the fifo enabled register bit will remain asserted if the lcl_enb input signal is set to false while the fifo is executing a dma transfer. in this case, the register bit will remain set for the duration of the dma transfer and then become cleared. bit 14: this bit is similar to the dma_req signal except that it is not blocked when dma_tc0 is set. it indicates that the programmed threshold has been met or exceeded and that the fifo requires data transfers either by enabling hardware dma through dma_tc0 or by executing software dma cycles.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 16-3 bit 13: this bit indicates that the fifo can accept data transfers to/from the local logic. this bit is low when the data direction is into the local logic and the fifo is empty or when the data direction is out of the local logic and the fifo is full. bit 12-10: this bit field indicates at which point the fifo should issue a dma request. it is compared with the fifo data quantity bit field to determine when this should occur. legal values are from 1 to 4. a value of zero causes no data transfers to occur. values greater than 4 are treated as 4. bit 9-8: this bit field indicates which byte of the fifo quad halfword structure is the next to be used as output data. bit 7: not used bit 6: this bit indicates that there is a full word in the holding register. bit 5: this bit indicates that there is a single byte in the holding register. bit 4-2: this bit field indicates the number of quad halfwords that contain data. valid values are from 0 to 4. bit 1-0: this bit field indicates which byte of the fifo quad halfword structure is the next to receive input data. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep1data (r/w) $01ff858d ep1 bulkin dataport register reset value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep1data (r/w) $01ff858c ep1 bulkin dataport register reset value 00h read value 00h bits 15-0: endpoint 1 fifo dataport register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep1tran (w) $01ff858f ep1 transition register reset. value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep1tran (w) $01ff858e ep1 transition register reset. value xxh
MFC2000 multifunctional peripheral controller 2000 hardware description 16-4 conexant 100723a bit 15-0: not used writing any value to this register causes a push or pop of data through the fifo data port and the fifo quad halfword 1-4 registers. the fifo operation depends on the direction of data flow. if system bus (cpu or dma) is writing (filling) the fifo, data is transferred from the fifo data port register to the fifo quad halfword 1 register, simultaneously with data transfer from quad halfword 1 to quad halfword 2, quad halfword 2 to quad halfword 3, and quad halfword 3 to quad halfword 4, with the original data of quad halfword 4 being lost. if the system bus is reading (emptying) the fifo, data is transferred from the fifo quad halfword 1 register to the fifo data port register, simultaneously with data transfer from quad halfword 2 to quad halfword 1, quad halfword 3 to quad halfword 2, and quad halfword 4 to quad halfword 3, with the contents of quad halfword 4 becoming indeterminate. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep2fifo1 (r/w) $01ff85a1 ep2 bulkout half word 1 rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep2fifo1 (r/w) $01ff85a0 ep2 bulkout half word 1 rst. value 00h read value 00h bits 15-0: endpoint 2 fifo quad half word 1 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep2fifo2 (r/w) $01ff85a3 ep2 bulkout half word 2 rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep2fifo2 (r/w) $01ff85a2 ep2 bulkout half word 2 rst. value 00h read value 00h bits 15-0: endpoint 2 fifo quad half word 2
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 16-5 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep2fifo3 (r/w) $01ff85a5 ep2 bulkout half word 3 rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep2fifo3 (r/w) $01ff85a4 ep2 bulkout half word 3 rst. value 00h read value 00h bits 15-0: endpoint 2 fifo quad half word 3 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep2fifo4 (r/w) $01ff85a7 ep2 bulkout half word 4 rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep2fifo4 (r/w) $01ff85a6 ep2 bulkout half word 4 rst. value 00h read value 00h bits 15-0: endpoint 2 fifo quad half word 4 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep2hold (r/w) $01ff85a9 ep2 bulkout holding register rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep2hold (r/w) $01ff85a8 ep2 bulkout holding register rst. value 00h read value 00h bits 15-0: endpoint 2 fifo holding register
MFC2000 multifunctional peripheral controller 2000 hardware description 16-6 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep2ctrl (r/w) $01ff85ab fifo enabled (read only) data request (read only) fifo ready fifo dma threshold fifo output pointer rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep2ctrl (r/w) $01ff85aa unused holding reg full byte present fifo data quantity fifo input pointer rst. value x0000000b read value 00h bit 15: this bit indicates that the fifo is active and capable of generating dma requests. this bit generally follows the setting of the lcl_enb input signal except the fifo enabled register bit will remain asserted if the lcl_enb input signal is set to false while the fifo is executing a dma transfer. in this case, the register bit will remain set for the duration of the dma transfer and then become cleared. bit 14: this bit is similar to the dma_req signal except that it is not blocked when dma_tc0 is set. it indicates that the programmed threshold has been met or exceeded and that the fifo requires data transfers either by enabling hardware dma through dma_tc0 or by executing software dma cycles. bit 13: this bit indicates that the fifo can accept data transfers to/from the local logic. this bit is low when the data direction is into the local logic and the fifo is empty or when the data direction is out of the local logic and the fifo is full. bit 12-10: this bit field indicates at which point the fifo should issue a dma request. it is compared with the fifo data quantity bit field to determine when this should occur. legal values are from 1 to 4. a value of zero causes no data transfers to occur. values greater than 4 are treated as 4. bit 9-8: this bit field indicates which byte of the fifo quad halfword structure is the next to be used as output data. bit 7: not used bit 6: this bit indicates that there is a full word in the holding register. bit 5: this bit indicates that there is a single byte in the holding register. bit 4-2: this bit field indicates the number of quad halfwords that contain data. valid values are from 0 to 4. bit 1-0: this bit field indicates which byte of the fifo quad halfword structure is the next to receive input data.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 16-7 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep2data (r/w) $01ff85ad ep2 bulkout dataport register rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep2data (r/w) $01ff85ac ep2 bulkout dataport register rst. value 00h read value 00h bits 15-0: endpoint 2 fifo data port register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep2tran (w) $01ff85af endpoint 2 tran rst. value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep2tran (w) $01ff85ae endpoint 2 tran rst. value xxh bit 15-0: not used writing any value to this register causes a push or pop of data through the fifo data port and the fifo quad halfword 1-4 registers. the fifo operation depends on the direction of data flow. if system bus (cpu or dma) is writing (filling) the fifo, data is transferred from the fifo data port register to the fifo quad halfword 1 register, simultaneously with data transfer from quad halfword 1 to quad halfword 2, quad halfword 2 to quad halfword 3, and quad halfword 3 to quad halfword 4, with the original data of quad halfword 4 being lost. if the system bus is reading (emptying) the fifo, data is transferred from the fifo quad halfword 1 register to the fifo data port register, simultaneously with data transfer from quad halfword 2 to quad halfword 1, quad halfword 3 to quad halfword 2, and quad halfword 4 to quad halfword 3, with the contents of quad halfword 4 becoming indeterminate.
MFC2000 multifunctional peripheral controller 2000 hardware description 16-8 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep3fifo1 (r/w) $01ff85b1 ep3 bulk-in half word 1 rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep3fifo1 (r/w) $01ff85b0 ep3 bulk-in half word 1 rst. value 00h read value 00h bits 15-0: endpoint 3 fifo quad half word 1 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep3fifo2 (r/w) $01ff85b3 ep3 bulk-in half word 2 rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep3fifo2 (r/w) $01ff85b2 ep3 bulk-in half word 2 rst. value 00h read value 00h bits 15-0: endpoint 3 fifo quad half word 2 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep3fifo3 (r/w) $01ff85b5 ep3 bulk-in half word 3 rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep3fifo3 (r/w) $01ff85b4 ep3 bulk-in half word 3 rst. value 00h read value 00h bits 15-0: endpoint 3 fifo quad half word 3
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 16-9 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep3fifo4 (r/w) $01ff85b7 ep3 bulk-in half word 4 rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep3fifo4 (r/w) $01ff85b6 ep3 bulk-in half word 4 rst. value 00h read value 00h bits 15-0: isocin fifo quad half word 4 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep3hold (r/w) $01ff85b9 ep3 bulk-in holding register rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep3hold (r/w) $01ff85b8 ep3 bulk-in holding register rst. value 00h read value 00h bits 15-0: endpoint 3 fifo holding register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep3ctrl (r/w) $01ff85bb fifo enabled (read only) data request (read only) fifo ready fifo dma threshold fifo output pointer rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep3ctrl (r/w) $01ff85ba unused holding reg full byte present fifo data quantity fifo input pointer rst. value x0000000b read value 00h bit 15: this bit indicates that the fifo is active and capable of generating dma requests. this bit generally follows the setting of the lcl_enb input signal except the fifo enabled register bit will remain asserted if the lcl_enb input signal is set to false while the fifo is executing a dma transfer. in this case, the register bit will remain set for the duration of the dma transfer and then become cleared. bit 14: this bit is similar to the dma_req signal except that it is not blocked when dma_tc0 is set. it indicates that the programmed threshold has been met or exceeded and that the fifo requires data transfers either by enabling hardware dma through dma_tc0 or by executing software dma cycles.
MFC2000 multifunctional peripheral controller 2000 hardware description 16-10 conexant 100723a bit 13: this bit indicates that the fifo can accept data transfers to/from the local logic. this bit is low when the data direction is into the local logic and the fifo is empty or when the data direction is out of the local logic and the fifo is full. bit 12-10: this bit field indicates at which point the fifo should issue a dma request. it is compared with the fifo data quantity bit field to determine when this should occur. legal values are from 1 to 4. a value of zero causes no data transfers to occur. values greater than 4 are treated as 4. bit 9-8: this bit field indicates which byte of the fifo quad halfword structure is the next to be used as output data. bit 7: not used bit 6: this bit indicates that there is a full word in the holding register. bit 5: this bit indicates that there is a single byte in the holding register. bit 4-2: this bit field indicates the number of quad halfwords that contain data. valid values are from 0 to 4. bit 1-0: this bit field indicates which byte of the fifo quad halfword structure is the next to receive input data. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep3data (r/w) $01ff85bd ep3 dataport register rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep3data (r/w) $01ff85bc ep3 dataport register rst. value 00h read value 00h bits 15-0: endpoint 3 fifo data port register
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 16-11 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep3tran (w) $01ff85bf ep3 transition register address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep3tran (w) $01ff85be ep3 transition register bit 15-0: not used writing any value to this register causes a push or pop of data through the fifo data port and the fifo quad halfword 1-4 registers. the fifo operation depends on the direction of data flow. if system bus (cpu or dma) is writing (filling) the fifo, data is transferred from the fifo data port register to the fifo quad halfword 1 register, simultaneously with data transfer from quad halfword 1 to quad halfword 2, quad halfword 2 to quad halfword 3, and quad halfword 3 to quad halfword 4, with the original data of quad halfword 4 being lost. if the system bus is reading (emptying) the fifo, data is transferred from the fifo quad halfword 1 register to the fifo data port register, simultaneously with data transfer from quad halfword 2 to quad halfword 1, quad halfword 3 to quad halfword 2, and quad halfword 4 to quad halfword 3, with the contents of quad halfword 4 becoming indeterminate. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep4fifo1 (r) $01ff85c1 ep4 fifo half word 1 reset. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep4fifo1 (r) $01ff85c0 ep4 fifo half word 1 reset. value 00h read value 00h bits 15-0: endpoint 4 fifo quad half word 1
MFC2000 multifunctional peripheral controller 2000 hardware description 16-12 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep4fifo2 (r) $01ff85c3 ep4 fifo half word 2 reset. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep4fifo2 (r) $01ff85c2 ep4 fifo half word 2 reset. value 00h read value 00h bits 15-0: endpoint 4 fifo quad half word 2 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep4fifo3 (r) $01ff85c5 ep4 fifo half word 3 reset value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep4fifo3 (r) $01ff85c4 ep4 fifo half word 3 reset. value 00h read value 00h bits 15-0: endpoint 4 fifo quad half word 3 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep4fifo4 (r) $01ff85c7 ep4 fifo half word 4 reset value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep4fifo4 (r) $01ff85c6 ep4 fifo half word 4 reset value 00h read value 00h bits 15-0: endpoint 4 fifo quad half word 4
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 16-13 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep4hold (r) $01ff85c9 ep4 fifo holding register reset value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep4hold (r) $01ff85c8 ep4 fifo holding register reset value 00h read value 00h bits 15-0: endpoint fifo holding register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep4ctrl (r/w) $01ff85cb fifo enabled (read only) data request (read only) fifo ready fifo dma threshold fifo output pointer reset value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep4ctrl (r/w) $01ff85ca unused holding register full byte present fifo data quantity fifo input pointer reset value 00h read value 00h bit 15: this bit indicates that the fifo is active and capable of generating dma requests. this bit generally follows the setting of the lcl_enb input signal except the fifo enabled register bit will remain asserted if the lcl_enb input signal is set to false while the fifo is executing a dma transfer. in this case, the register bit will remain set for the duration of the dma transfer and then become cleared. bit 14: this bit is similar to the dma_req signal except that it is not blocked when dma_tc0 is set. it indicates that the programmed threshold has been met or exceeded and that the fifo requires data transfers either by enabling hardware dma through dma_tc0 or by executing software dma cycles. bit 13: this bit indicates that the fifo can accept data transfers to/from the local logic. this bit is low when the data direction is into the local logic and the fifo is empty or when the data direction is out of the local logic and the fifo is full. bit 12-10: this bit field indicates at which point the fifo should issue a dma request. it is compared with the fifo data quantity bit field to determine when this should occur. legal values are from 1 to 4. a value of zero causes no data transfers to occur. values greater than 4 are treated as 4. bit 9-8: this bit field indicates which byte of the fifo quad halfword structure is the next to be used as output data. bit 7: not used bit 6: this bit indicates that there is a full word in the holding register.
MFC2000 multifunctional peripheral controller 2000 hardware description 16-14 conexant 100723a bit 5: this bit indicates that there is a single byte in the holding register. bit 4-2: this bit field indicates the number of quad halfwords that contain data. valid values are from 0 to 4. bit 1-0: this bit field indicates which byte of the fifo quad halfword structure is the next to receive input data. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep4data (r/w) $01ff85cd ep4 endpoint dataport register reset value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep4data (r/w) $01ff85cc ep4 endpoint dataport register reset value 00h read value 00h bits 15-0: endpoint 4 fifo data port register address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep4tran (w) $01ff85cf ep4 transition register address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep4tran (w) $01ff85ce ep4 transition register bit 15-0: not used writing any value to this register causes a push or pop of data through the fifo data port and the fifo quad halfword 1-4 registers. the fifo operation depends on the direction of data flow. if system bus (cpu or dma) is writing (filling) the fifo, data is transferred from the fifo data port register to the fifo quad halfword 1 register, simultaneously with data transfer from quad halfword 1 to quad halfword 2, quad halfword 2 to quad halfword 3, and quad halfword 3 to quad halfword 4, with the original data of quad halfword 4 being lost. if the system bus is reading (emptying) the fifo, data is transferred from the fifo quad halfword 1 register to the fifo data port register, simultaneously with data transfer from quad halfword 2 to quad halfword 1, quad halfword 3 to quad halfword 2, and quad halfword 4 to quad halfword 3, with the contents of quad halfword 4 becoming indeterminate.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 16-15 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep0buf2 (r/w) $01ff85d1 ep0 buffer 2 rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep0buf1 (r/w) $01ff85d0 ep0 buffer 1 rst. value 00h bits 15-8: 2 nd data byte of endpoint 0 buffer bits 7-0: 1 st data byte of endpoint 0 buffer address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep0buf4 (r/w) $01ff85d3 ep0 buffer 4 rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep0buf3 (r/w) $01ff85d2 ep0 buffer 3 rst. value 00h bits 15-8: 4th data byte of endpoint 0 buffer bits 7- 0: 3rd data byte of endpoint 0 buffer address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep0buf6 (r/w) $01ff85d5 ep0 buffer 6 rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep0buf 5 (r/w) $01ff85d4 ep0 buffer 5 rst. value 00h bits 15-8: 6th data byte of endpoint 0 buffer bits 7- 0: 5th data byte of endpoint 0 buffer
MFC2000 multifunctional peripheral controller 2000 hardware description 16-16 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep0buf8 (r/w) $01ff85d7 ep0 buffer 8 rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep0buf7 (r/w) $01ff85d6 ep0 buffer 7 rst. value 00h bits 15-8: 8th data byte of endpoint 0 buffer bits 7- 0: 7th data byte of endpoint 0 buffer address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep5buf2 (r/w) $01ff85d9 ep5 buffer 2 rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep5buf1 (r/w) $01ff85d8 ep5 buffer 1 rst. value 00h bits 15-8: 2 nd data byte of endpoint 5 buffer bits 7- 0: 1 st data byte of endpoint 5 buffer address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep5buf4 (r/w) $01ff85db ep5 buffer 4 rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep5buf3 (r/w) $01ff85da ep5 buffer 3 rst. value 00h bits 15-8: 4 th byte of the endpoint 5 buffer bits 7-0: 3 rd byte of the endpoint 5 buffer
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 16-17 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep5buf6 (r/w) $01ff85dd ep5 buffer 6 rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep5buf5 (r/w) $01ff85dc ep5 buffer 5 rst. value 00h bits 15-8: 6 th byte of the endpoint 5 buffer bits 7-0: 5 th byte of the endpoint 5 buffer address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep5buf8 (r/w) $01ff85df ep5 buffer 8 rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep5buf7 (r/w) $01ff85de ep5 buffer 7 rst. value 00h bits 15-8: 8 th byte of the endpoint 5 buffer bits 7-0: 7 th byte of the endpoint 5 buffer address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep5stdat2 (r) $01ff85e1 ep5 setup packet data 2 nd byte rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep5stdat1 (r) $01ff85e0 ep5 setup packet data 1 st byte rst. value 00h read value 00h bits 15-8: 2 nd data byte of the setup packet for ep5 bits 7:0: 1 st data byte of the setup packet for ep5
MFC2000 multifunctional peripheral controller 2000 hardware description 16-18 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep5stdat4 (r) $01ff85e3 ep5 setup packet data 4 th byte rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep5stdat3 (r) $01ff85e2 ep5 setup packet data 3 rd byte rst. value 00h read value 00h bits 15-8: 4 th data byte of the setup packet for ep5 bits 7:0: 3 rd data byte of the setup packet for ep5 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep5stdat6 (r) $01ff85e5 ep5 setup packet data 6 th byte rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep5stdat5 (r) $01ff85e4 ep5 setup packet data 5 th byte rst. value 00h read value 00h bits 15-8: 6 th data byte of the setup packet for ep5 bits 7:0: 5 th data byte of the setup packet for ep5 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep5stdat8 (r) $01ff85e7 ep5 setup packet data 8 th byte rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep5stdat7 (r) $01ff85e6 ep5 setup packet data 7 th byte rst. value 00h read value 00h bits 15-8: 8 th data byte of the setup packet for ep5 bits 7:0: 7 th data byte of the setup packet for ep5
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 16-19 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbirq (r) $01ff85e9 ep4 interrupt ep2 interrupt suspend status ep5 write ack ep5 read ack ep0 write ack ep0 read ack usb reset interrupt rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbirq (r) $01ff85e8 suspend interrupt dma interrupt ep5 write interrupt ep5 read interrupt ep5 setup interrupt ep0 write interrupt ep0 read interrupt ep0 setup interrupt rst. value 00h bit 15: this bit indicates that an odd packet is received at endpoint 4. bit 14: this bit indicates that an odd packet is received at endpoint 2. bit 13: when it is ?1?, it indicates that the device is in suspend mode. if the pc does a global wake up, this bit will be reset to ?0?. the firmware can reset this bit to ?0? by performing a device remote wakeup (setting the resume bit to be ?1? in usbclrirq register). bit 12: this bit indicates that if the control write on endpoint 5 is successful. ?1? ? ack. ?0? ? nack. bit 11: this bit indicates that if the control read on endpoint 5 is successful. ?1? ? ack. ?0? ? nack. bit 10: this bit indicates that if the control write on endpoint 0 is successful. ?1? ? ack. ?0? ? nack. bit 9: this bit indicates that if the control read on endpoint 0 is successful. ?1? ? ack. ?0? ? nack. bit 8: this bit indicates that a usb reset is detected on the bus. bit 7: this bit indicates a suspend is detected on the bus. bit 6: this bit indicates the dma has reached its block size. bit 5: this bit indicates that the endpoint 5 data buffer is full. bit 4: this bit indicates that the data in endpoint 5 buffer has been send. bit 3: this bit indicates that a set up packet has been send to endpoint 5 and the endpoint 5 setup data buffer is full. bit 2: this bit indicates that the endpoint 0 data buffer is full. bit 1: this bit indicates that the data in endpoint 0 buffer has been send. bit 0: this bit indicates that a set up packet has been send to endpoint 5 and the endpoint 5 setup data buffer is full.
MFC2000 multifunctional peripheral controller 2000 hardware description 16-20 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbclrirq (r/w) $01ff85eb unused clear ep4 interrupt clear ep2 interrupt clear usb reset interrupt ep5 write buffer read ep5 read buffer written ep0 write buffer read ep0 read buffer written rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbclrirq (r/w) $01ff85ea clear suspend interrupt resume device clear ep5 write interrupt clear ep5 read interrupt clear ep5 setup interrupt clear ep0 write interrupt clear ep0 read interrupt clear ep0 setup interrupt rst. value 00h bit 15: unused bit 14: set this bit to ?1? to clear the endpoint 4 interrupt. bit 13: set this bit to ?1? to clear the endpoint 2 interrupt. bit 12: set this bit to ?1? to clear the usb reset interrupt. bit 11: set this bit to ?1? to indicate that the endpoint 5 buffer is empty. bit 10: set this bit to ?1? to indicate that the endpoint 5 buffer is full. bit 9: set this bit to ?1? to indicate that the endpoint 0 buffer is empty. bit 8 set this bit to ?1? to indicate that the endpoint 0 buffer is full. bit 7: set this bit to ?1? to clear the suspend interrupt. bit 6: set this bit to ?1? to perform device remote wake-up. bit 5: set this bit to ?1? to clear endpoint 5 write interrupt. bit 4: set this bit to ?1? to clear endpoint 5 read interrupt. bit 3: set this bit to ?1? to clear endpoint 5 setup interrupt. bit 2: set this bit to ?1? to clear endpoint 0 write interrupt. bit 1: set this bit to ?1? to clear endpoint 0 read interrupt. bit 0: set this bit to ?1? to clear endpoint 0 setup interrupt. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbsofreset (w) $01ff85ed unused rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbsofreset (w) $01ff85ec unused software reset rst. value 01h bit 15:1: not used bit 0: set this bit to ?1? reset usb interface block.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 16-21 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbstall (r/w) $01ff85ef unused rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbstall(r/w) $01ff85ee unused ep5 stalled ep4 stalled ep3 stalled ep2 stalled ep1 stalled ep0 stalled rst. value 01h bit 15:6: not used bit5: set this bit to ?1? to indicate that the endpoint 5 is stalled. bit4: set this bit to ?1? to indicate that the endpoint 4 is stalled. bit3: set this bit to ?1? to indicate that the endpoint 3 is stalled. bit2: set this bit to ?1? to indicate that the endpoint 2 is stalled. bit1: set this bit to ?1? to indicate that the endpoint 1 is stalled. bit0: set this bit to ?1? to indicate that the endpoint 0 is stalled. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep0stdat2 (r) $01ff85f1 ep0 setup packet data 2 nd byte rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep0stdat1 (r) $01ff85f0 ep0 setup packet data 1 st byte rst. value 00h bits 15-8: 2 nd data byte of the setup packet for ep0 bits 7:0: 1 st data byte of the setup packet for ep0 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep0stdat4 (r) $01ff85f3 ep0 setup packet data 4 th byte rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep0stdat3 (r) $01ff85f2 ep0 setup packet data 3 rd byte rst. value 00h bits 15-8: 4 th data byte of the setup packet for ep0 bits 7:0: 3 rd data byte of the setup packet for ep0
MFC2000 multifunctional peripheral controller 2000 hardware description 16-22 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep0stdat6 (r) $01ff85f5 ep0 setup packet data 6 th byte rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep0stdat5 (r) $01ff85f4 ep0 setup packet data 5 th byte rst. value 00h bits 15-8: 6 th data byte of the setup packet for ep0 bits 7:0: 5 th data byte of the setup packet for ep0 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: usbep0stdat8 (r) $01ff85f7 ep0 setup packet data 8 th byte rst. value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: usbep0stdat7 (r) $01ff85f6 ep0 setup packet data 7 th byte rst. value 00h bits 15-8: 8 th data byte of the setup packet for ep0 bits 7:0: 7 th data byte of the setup packet for ep0
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 16-23 16.3 firmware operation 16.3.1 setup transfer during the setup transfer, a setup interrupt will be generated to the arm. arm can determine it is a setup interrupte by reading the interrupt register and clear the interrupt by setting the clear endpoint 0 or 5 setup interrupt bit of the usbclrirq register. the 8 bytes of setup packet data can be read from the endpoint 0 or 5 setup buffer. 16.3.1.1 usb standard commands since the udc core decodes and acts upon the usb standard commands except get_descriptor, the setup packet data of all standard commands (except get_descriptor ) will not be stored in the setup buffers neither the setup interrupt will be generated during a starndard command transfer. 16.3.1.2 get_descriptor command the get_descriptor command is supported by endpoint 0. the arm needs to decode the setup packet and load the descriptor data into the endpoint 0 buffer then set the ep0 read buffer written bit. 16.3.2 control read transfer during a control read transfer, an interrupt will be generated along with read status bit after the data in the ep0/ep5 buffer are send to the host. arm can determine the type of interrupt by reading the interrupt register and clear the interrupt by setting the corresboing bit in the clear interrupt register. arm needs to check the ep0/ep5 read status bit to find out if the control read is successful or not. 16.3.3 control write transfer during a control write transfer, the data from the pc will be written to an internal buffer first. after the control write transfer finished, an interrupt along with write status bit will be generated. arm can determine the interrupt by reading the interrupt register and clear the interrupt by writing to the corresbonding bit in the clear_interrupt register. then arm can read data from the endpoint 0 or endpoint 5 data buffers. after all the data have been read , arm will set the endpoint 0 or endpoint 5 write_buffer_read bit in the endpoint status register. 16.3.4 bulk_in transfer the maxpacketsize for both bulk in pipes are 64 bytes. dma channel 0 is assigned to usb and it has four logic channels. endpoint 1 and 3, which are bulk in endpoints, are assigned to logic channel 0 and 2. the procedures of programming the registers are: 1. enable dma channel 0 by writing 1 to bit[0] of dma 0 configuration register. 2. enable logic channel 0 or 2 and set logic channel 0 or 2 to be read mode by setting the corresbonding bits in dma 0 configuration register. 3. set memory address in dmausb0cntlo and dmausb0cnthi or dmausb2cntlo and dmausb2cnthi. 4. define block size in dmausb0blksiz or dmausb2blksiz. 5. if more than one memory block is needed, repeat step 3 and 4 to set desired memory blocks. 6. load 4 half words into endpoint 1 or 3 internal fifo by writing to endpoint 1 or 3 data port register and transition register or by writing to the endpoint 1 or 3 halfword fifos. 7. set endpoint 1 or 3 control register.
MFC2000 multifunctional peripheral controller 2000 hardware description 16-24 conexant 100723a if the pc has read all the data in the memory blocks successfully, an interrupt will be generated. arm can read the usbirq register to determine that it is dma channel 0 interrupt. by reading dma 0 configuration register can determine it is a logic channel 0 or 2 interrupt. then arm can repeat step 3 and 4 to set more memory blocks. 1.1.5 16.3.5 bulk_out transfer the maxpacketsize for both bulk in pipes are 64 bytes. dma channel 0 is assigned to usb and it has four logic channels. endpoint 2 and 4, which are bulk out endpoints, are assigned to logic channel 1 and 3. the procedures of programming the registers are: 1. enable dma channel 0 by writing 1 to bit[0] of dma 0 configuration register. 2. enable logic channel 1 or 3 and set logic channel 1 or 3 to be write mode by setting the corresbonding bits in dma 0 configuration register. 3. set memory address in dmausb1cntlo and dmausb1cnthi or dmausb3cntlo and dmausb3cnthi. 4. define block size in dmausb1blksiz or dmausb3blksiz. 5. if more than one memory block is needed, repeat step 3 and 4 to set desired memory blocks. 6. set endpoint 2 or 4 control register. if the pc has write to all the memory blocks successfully, an interrupt will be generated. arm can read the usbirq register to determine that it is dma channel 0 interrupt. by reading dma 0 configuration register can determine it is a logic channel 1 or 3 interrupt. then arm can repeat step 3 and 4 to set more memory blocks. if the pc send an odd byte count packet in the middle of a bulkout transaction, an interrupt will be generated to indicate that an single byte has been send to the memory location. 1.1.6 16.3.6 usb suspend and device remote wake-up the MFC2000 supports device remote wake-up. if the udc core detected the usb bus being idle for 3 ms, it will generated a suspend signal and an interrupt will be generated. arm can determine that it is a suspend interrupt by reading the usb interrupt register then clear the interrupt by setting the clear_suspend_int bit in the clear interrupt register. the suspend status bit will remain high until the pc performs a global wake up or the arm performs a device remote wake up. the arm performs a device remote wake up by setting the resume_device bit in the endpoint status register to be ?1?. 1.1.7 16.3.7 usb reset an interrupt will be generated if a usb reset is detected on the usb bus. arm can determine that it is a usb_reset_interrupt by reading the usb interrupt register then clear the interrupt by setting the clear_usb_reset_int bit in the clear interrupt register. 1.1.8 16.3.8 software reset the arm can reset the udc core and related logic by setting the bit 0 in usbsofreset register.
multifunctional peripheral controller 2000 MFC2000 100723a conexant 17-1 17. bi-directional parallel peripheral interface the parallel peripheral interface(ppi) controller incorporates the ieee-1284 compatibility/nibble/ byte/ ecp protocols to offer flexible high-speed parallel data transfer. furthermore, the ppi fully supports all variants of these modes, including device id requests and run-length encoded data compression. all protocols are signal- compatible with classic parallel interfaces. the default protocol for the ppi is the compatibility mode. the ppi contains specific hardware to support automatic handshaking during host to peripheral,or forward, data transfers in compatible and ecp modes, and run-length detection. the ppi also supports automatic handshaking during peripheral to host, or reverse, data transfers in the nibble, byte and ecp modes. the hardware handshaking can also be completely disabled to allow software to directly control the peripheral port interface signals and to support new protocols as they arise in the future. 17.1 operational modes the ppi supports three hardware handshaking modes for host to peripheral, or forward, data transfers. each mode can be enabled or disabled by software. one mode supports forward data transfers during compatibility mode, and the other two modes support forward data transfers during ecp mode. only one of the three modes can be enabled at a time, or all modes can be disabled. when disabled, software must assume full responsibility for handshaking, and use the parallel port interface register and the parallel port data register to read and control the logic levels on all parallel port pins. the hardware handshaking modes for peripheral to host, or reverse, data transfers are provided for nibble, byte and ecp modes explained. 17.1.1 compatibility mode the interface is always initialized to the compatibility mode, a conventional, unidirectional host-to peripheral interface. from the compatibility mode the host may transmit data to peripheral or direct the interface to a mode capable of transmitting data to the host. compatibility mode hardware handshaking is enabled by setting the mode field to 1 in the parallel port control register. when compatibility mode is selected, the ppi interacts with host using stroben, busy and ackn signals. 17.1.2 p1284 negotiation the negotiation phase is performed under firmware control. during the negotiation, the firmware will respond to the host stimulus by setting ackn low, faultn high, slctout(xflag) high, pe high as defined in the ieee 1284 specification. after the host responds to the prior signal setting, the firmware will respond with a pe low and a faultn low if data to the host is available. the slctout is set to it?s appropriate value corresponding to the extensibility feature requested by the host. (refer to the ieee 1284 specification for a more complete definition of this phase). 17.1.3 nibble mode provides an asynchronous, reverse (peripheral-to-host) channel, under control of the host. data bytes are transmitted as two sequential, four bit nibbles using four peripheral-to-host status lines. in nibble mode(mode=4), one byte of status data can be put to the ppi data register by cpu or dma operation. the ppi logic will separate the one byte data into two nibbles and send them in sequence. the signals used in the nibble mode are autofdn and ackn for handshake and faultn, slctout, pe and busy for data transfer. 17.1.4 byte mode provides an asynchronous, byte-wide reverse peripheral-to-host channel using eight data lines of the interface for data and the control/status lines for handshaking. the ppi hardware can control the handshake of the reverse data transfer. the cpu must provide the status to send the next byte or to terminate the protocol. the mode=5 for the byte mode which enables a peripheral to send an entire byte of data to the pc in one data transfer cycle using the 8 data lines, rather than the two cycles using the nibble mode.the handshake signals are autofdn, ackn and stroben.
MFC2000 multifunctional peripheral controller 2000 hardware description 17-2 conexant 100723a 17.1.5 ecp forward extended capabilities port (ecp) mode provides an asynchronous, byte-wide, bi-directional channel. the data can be received by dma mode or cpu mode as described in the compatibility mode section. the ecp protocol provides the data and command cycles types in both forward and reverse directions. the mode = 2 and 3 for the forward mode with rle . when mode is set to 2, ecp mode hardware handshaking is enabled during forward data transfers, without rle support. when mode 2 is programmed, the ppi responds to a high to low transition on stroben (hostclk), and automatically sets and clears the busy bit in the parallel port interface register and the busy to handshake with the host.. mode may be reprogrammed at any time, but if an ecp cycle is currently in progress, it completes as normal. 17.1.6 ecp reverse after a successful forward to reverse phase switch, the ecp changes into the reverse phase in mode = 6. when the 1284 interface is idle, this is the desired mode of operation. this mode will allow the MFC2000 asic to inform the host of incoming fax data. the ecp reverse mode can operate under cpu interrupt driven control or automated dma control. in cpu control, the software writes the outgoing byte into the output buffer and then sets ackn low to send the data. after the host completes the data transfer, the ackn is automatically set high and the cpu is free to respond to any ppi interrupts that have been enabled or to initiate an additional data transfer if needed. the handshake signals are initn, pe, ackn, autofdn and busy. 17.1.7 the non-standard dribble mode the dribble mode was used for the slower pc before p1284 is standardized. dribble mode is similar to ecp in that the channel can be reversed without having to go through a negotiation phase to turn the channel around. it sends two bits at a time on the nperiphrequest and xflag signals rather than using the pio data bus. in this respect, it is similar to nibble mode's data transfer phase in that it uses hostbusy and ptrclk to transfer each portion of the data byte. the dribble mode can only operate under cpu interrupt-driven control (no dma mode). note : this is not an ieee-1284 mode but is useful to support certain product interfaces created prior to the ieee-1284 specification. 17.2 additional features 17.2.1 filter a digital filter is provided for incoming host control and data signals. slctinn, stroben, autofdn, and initn are provided with digital filter circuits which are collectively controlled by software. if dfil =0, then no digital filtering is selected. note that synchronization plus digital filtering adds up to four clk periods of delay before a level change at one of the host inputs appears in the parallel port control register, and five periods of delay before an output responds to an input (e.g., before busy responds to stroben). likewise, synchronization and digital filtering of stroben affect the point at which ippid[7-0] and autofdn are latched into the parallel port data register. without a dfil=3, ippid[7-0] and autofdn are sampled an the fourth rising edge of clk after stroben is sampled. with digital filtering, ippid7-0 and autofdn are sampled on the fifth rising edge of clk after stroben is sampled.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 17-3 17.3 functional description the ppi contains an interface controller, which consists of: a data receive and transmit latch, run-length encoding decompression logic, input conditioning logic, and edge detector logic. the rle decompression is accomplished through a state machine and additional control logic. there is input conditioning logic to filter the incoming control signals. the peripheral interface block supports four ieee 1284 communication modes: compatibility, nibble, byte, and enhanced capabilities port (ecp) mode. the interface with the dma controller requires storing data into 8 bit bytes before transferring to the four half word fifo for burst operation. there will be a counter within the fifo that keeps track of the bytes transferred to the fifo. there is a control bit allowing fifo flush to be done. if firmware detects the end of transfer to the ppi, it can flush the fifo by forcing the flush bit. the timing of the f/w flush is based on a fixed time from the last dma access and the fifo not empty status and there will be a busy status bit set by f/w to stop further transmission from the host. the dma or the interrupt operations are enabled under the control of the f/w. the ppi has fifteen sources of interrupt that can each be individually enabled or disabled and they are all ored together to generate one ppi irq interrupt for the cpu. data receive latch slctinn stroben autofdn initn state machine sinb control registers data transmit latch faultn slctoutn pe ackn busy ippid(7:0) fppd(7:0) rppd(7:0) oppid(7:0) strb afdb inib digital filter dma fifos ip_bus fack rreq rack ip_bus dmareq dmarwn dmaack dma_tc freq figure 17-1. parallel port interface controller block diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 17-4 conexant 100723a 17.4 register description parallel port control register address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default parallel port control reg. (pioctrl) $01ff8201 (not used) (not used) trizn ppirstn mode mode rfull (r) ffull (r) rst. value xx000000b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default parallel port control reg. (pioctrl) $01ff8200 rld (r) abrt pdoe (r) errc mode mode dfil dfil rst. value 00h read value 00h dfil digital filter this 2 bit field controls the number of clocks of digital filtering to be applied on the four host control signal inputs, slctinn, stroben, autofdn, and initn. from 0 to 3 clocks of digital filtering may be selected. mode mode this 4 bit field(bits 11,10,3,2) selects and enables a hardware handshaking mode for forward data transfers. mode direction function 0 disable 1 fwd compatibility mode 2 fwd ecp-fwd without rle mode 3 fwd ecp-fwd with rle mode 4 rev nibble mode 5 rev byte mode 6 rev ecp-rev mode 7 rev dribble mode 8-15 reserved error cycles this bit is used to execute an error cycle when in compatibility mode (mode 1). when set, errc immediately forces the busy pin high. if errc is set when a compatibility mode handshake sequence is in process, the busy remains high beyond the end of the cycle. errc does not affect an ackn pulse that is already active, but does prevent an ackn pulse if it is about to be generated. while errc is set, software may set or clear sel, perr, and nflt in the parallel port interface register. when errc is cleared, the ppi generated an ackn pulse and tries to lower busy to conclude the error cycle. if, however, fbsy is set, busy remains high until fbsy is cleared. when mode is set to any value except 1, setting errc has no effect. setting mode to 1 when errc is already set causes the handshake controller to immediately begin an error cycle.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 17-5 pdoe parallel data output enable this bit performs two functions. it controls the state of the pd bus three-state output drives, and it qualifies the latching of data from the pd bus into the parallel port data register. when set, pdoe enables the pd bus output pin drivers, and prevents data from being latched into the parallel port register. setting abrt affects the operation of pdoe. if abrt is set, slctinn (1284active) must remain high to allow pdoe to be set or remain set. if abrt is set and slctinn (1284active) goes low, pdoe is cleared, and setting pdoe has no effect. abrt abort this causes the ppi to use slctinn (1284active) to detect when the host suddenly aborts a reverse transfer and returns to compatibility mode. if abrt is set, a low level on slctinn (1284 active) causes pdoe to be cleared and the pd bus output drivers to be three-stated. in fact, if abrt is set and slctinn (1284active) is low, setting pdoe has no effect. this protection logic, as all internal logic, operates from a synchronized and optionally digitally filtered slctinn (1284active) that is latched into the parallel port interface register. rld run length decompression this is a read-only status bit which indicates when run-length decompression is taking place during ecp forward data transfers. rld is set when a run-length count is received and loaded into the internal counter, and cleared when the last read of the parallel port data register takes place. this bit can only be set when ecp with rle (mode 3) is enabled. if mode is reprogrammed during a decompression, decompression continues and rld remains set until the operation is completed. rld is cleared when rst is issued. ffull forward data register full this is a read-only status bit that indicates when parallel port data from the host is latched in the parallel port data register. ffull is cleared when the parallel port data register is read. when handshaking and dma is enabled, ffull sets and clears as data is latched and read during forward data transfers. ffull is also cleared when rst is issued. rfull reverse data register full this is a read-only status bits indicates when parallel port data to the host is latched in the parallel port data register. rfull is cleared when the parallel port data register is sent. when handshaking and dma is enabled, rfull sets and clears as data is latched and sent during reverse data transfers. rfull is also cleared when rst is issued. ppirstn parallel port software reset active low resets all the state machines and is programmable using this register bit. during the normal operation this bit needs to be set to allow the state machine to start. trizn tri-state output enable active low to enable tri-state input during the forward(pc to printer) transfers.
MFC2000 multifunctional peripheral controller 2000 hardware description 17-6 conexant 100723a parallel port interface register the parallel port interface register is a read/write register that contains eleven bits to control the parallel port interface signals. four read-only bits are used to read the logic level of host input pins, two read-only bits are used to read the logic level on the busy and ackn printer output pins, and five read/write bits control the logic levels on the printer output pins. when hardware handshaking is enabled(mode 1,2,3) busy and ackn are controlled by the ppi state machine. when hardware handshaking is disabled (mode 0) and the ppi state machine is idle busy and ackn may be controlled by the software using the fbsy and fack bits. note: nflt,sel,perr and fbsy are arranged as register bits 0, 1, 2, and 3, respectively, to correspond to their use as parallel data lines during nibble mode reverse data transfers. address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default parallel port interface reg. (pioif) $01ff8203 (not used) frda sper (r) ssel (r) snfl (r) nini (r) nafd (r) nstr (r) rst. value x0000000b read value 07h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default parallel port interface reg. (pioif) $01ff8202 nsin (r) nack (r) busy (r) fack fbsy perr sel nflt rst. value 08h read value 08h nflt faultn this bit controls the logic level driven on faultn output pin. setting nflt drives a high level and clearing sel drives a low level. sel slctout this controls the logic level driven on the slctout output pin. setting sel drives a high level and clearing sel drives a low level. perr paper error this bit controls the logic level driven on the pe output pin. setting perr drives a high level and clearing perr drives a low level. fbsy force busy this bit force a high level to be driven on the busy output pin. normally this is done when hardware handshaking is disabled(mode 0), and the ppi state machine is idle. the fbsy bit is or?ed with the busy output from the ppi state machine before driving the busy output pin. if fbsy is set, then the busy output pin is forced high, and the busy bit is read high. this bit is set on reset. fack force ack this bit forces a low level to be driven on the ackn output pin. normally this is done when hardware handshaking is disabled (mode 0), and the ppi state machine is idle. the fack bit is nor?ed with the ackn output from the ppi state machine before driving the ackn output pin. if fack is set, then the ackn output pin is forced low, and the nack bit is to be read low. busy this status bit indicates the level driven on the busy output pin. this bit is the fbsy bit or?ed with busy output from the ppi state machine. since fbsy is set on reset, this bit will appear set on reset. this is a read-only status bit.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 17-7 nack ackn this status bit indicates the level driven on the ackn output pin. this bit is the fack bit nor?ed with the ackn output from the ppi state machine. since fack is cleared on reset, this bit will appear set on reset. this is read-only status bit. nsin slctinn this status bit indicates the level read on the slctinn* input pin after synchronization and optional digital filtering. this is a read-only status bit. nstr strobe* this status bit indicates the level read on the strobe* input pin after synchronization and optional digital filtering. this is a read-only status bit. nafd autofdn this status bit indicates the level read on the autofdn input pin after synchronization and optional digital filtering. this is a read-only status bit. nini initn this status bit indicates the level read on the initn input after synchronization and optional digital filtering. this is a read-only status bit. snfl faultn status this status bit indicates the level read on the faultn output pin. this is a read-only status bit. ssel slctout status this status bit indicated the level read on the slctout output pin. this is a read-only status bit. sper paper error status this status bit indicated the level read on the pe output pin. this is a read-only status bit. frda force reverse data available this bit controls the rda status during nibble mode and byte mode when dma is not used. parallel port data register the parallel port data register is a 9-bit read/write register that is used to control the parallel port data bus. reading this register provides the latched logic levels at pd7-0 and autofdn pin. data is latched on every high to low transition of stroben (hostclk), when pdoe is clear in the parallel port control register. if pdoe is set, the parallel port data register is frozen, and unaffected by the transitions on stroben. reading this register clears the full bit, and clears the pdma request. this register should not be read while the pdma channel is enabled. address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default parallel port data reg. (piodata) $01ff8205 (not used) (not used) (not used) (not used) (not used) (not used) (not used) ncmd rst. value xxxxxxx0b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default parallel port data reg. (piodata) $01ff8204 data(7) data(6) data(5) data(4) data(3) data(2) data(1) data(0) rst. value 00h read value 00h data data this field is an 8-bit read/write field. when used, data provides the latched logic levels on pd7-0 when stroben (hostclk) last transmitted from high to low with pdoe clear. when written, the data value defines the logic levels to be driven by the qp1700 when pd7-0 is enabled by the pdoe bit. the most significant bit of the data field corresponds to pd7 and the least significant bit to pd0.
MFC2000 multifunctional peripheral controller 2000 hardware description 17-8 conexant 100723a ncmd command when read, this bit provides the logic level of the autofdn pin when stroben (hostclk) transitioned from high to low with pdoe clear. if set, autofdn was latched high. if low, autofdn was latched low. this is a read-only data bit. writing ncmd has no effect. parallel port ack pulse width register the parallel port ack pulse width register is an 8-bit read/write register that defines the pulse width of ackn during compatibility mode (mode = 1), and setup timing relative to ackn during reverse transfer modes (mode=4,4,6). the parallel port ackn pulse width register can be written and rewritten to program different timing values as transitions are made to new transfer modes. an ackn pulse width can be programmed to be 0 to 255 ihsclk periods wide. at 20mhz, this allows software to set pulse widths anywhere in the range of 0 to 12.75us. if ackw is set to zero, no ackn pulse is generated at the end of compatibility mode cycles. setup timing relative to ackn during reverse transfer modes can be programmed to be 1 to 256 ihsclk periods. during nibble or byte modes(mode=4,5), ackw defines the setup timing from nibble or byte data (event 8 or 15) and the falling edge of ackn (event 9), or from peripheral status (event 13) to the rising edge of ackn (event 11). during ecp reverse transfers (mode = 6), ackw defines the setup timing from reverse data (event 42) to the falling edge of ackn (event 43). address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default parallel port ack pulse width reg. (pioackpw) $01ff8207 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default parallel port ack pulse width reg. (pioackpw) $01ff8206 ackw(7) ackw(6) ackw(5) ackw(4) ackw(3) ackw(2) ackw(1) ackw(0) rst. value 00h read value 00h ackw ackn pulse width this 8 bit field defines the pulse width of ackn during compatibility mode transfers (mode = 1), and the setup relationship relative to ackn during reverse transfer modes (mode=4,5,6). a pulse width from 0 to 255 ihsclk periods can be programmed. parallel port reverse data status register address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default parallel port reverse data status reg. (piorevdatasts) $01ff8209 (r) (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default parallel port reverse data status reg. (piorevdatasts) $01ff8208 (r) rvdat(7) rvdat(6) rvdat(5) rvdat(4) rvdat(3) rvdat(2) rvdat(1) rvdat(0) rst. value 00h read value 00h revdata reverse data this 8-bit field is the status of the reverse data that was written into the parallel port data register oppid[7:0]. this normally is needed only for diagnostic purposes. this is a read-only status register.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 17-9 parallel port data bus status register address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default parallel port data bus status reg. (piodatabussts) $01ff820b (r) (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default parallel port data bus status reg. (piodatabussts) $01ff820a (r) pdbus(7) pdbus(6) pdbus(5) pdbus(4) pdbus(3) pdbus(2) pdbus(1) pdbus(0) rst. value 00h read value 00h ppdbus data bus status this 8 bit field is the status of the parallel port data bus ippid[7:0]. this normally is needed only for diagnostic purposes. this is a read-only status register. parallel port host timeout register address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default parallel port host timeout reg. (piohosttimeout) $01ff820d (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default parallel port host timeout reg. (piohosttimeout) $01ff820c htim(7) htim(6) htim(5) htim(4) htim(3) htim(2) htim(1) htim(0) rst. value 00h read value 00h htim host timeout this 8 bit field controls the timer for the host timeout error interrupt hte. the timer counts from the system timer which is usually programmed to count every 8 msec. httm is usually programmed with a value of 0x7d (125) so that a host timeout interrupt occurs after 1 sec. if the host timeout error interrupt hte is not desired, then interrupt enable should be false.
MFC2000 multifunctional peripheral controller 2000 hardware description 17-10 conexant 100723a interrupt status register address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default parallel port interrupt status (pioirqsts) $01ff820f (not used) dmarirq dmafirq hte rdx ivt crx drx rst. value x0000000b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default parallel port interrupt status (pioirqsts) $01ff820e inil inih afdl afdh strl strh sinl sinh rst. value 00h read value 00h sinh slctinn high edge interrupt. sinl slctinn low edge interrupt. strh stroben high edge interrupt. strl stroben low edge interrupt. afdh autofdn high edge interrupt. afdl autofdn low edge interrupt. inih initn high edge interrupt. inil initn low edge interrupt. drx data received interrupt. crx command received interrupt. ivt invalid transition interrupt. rdx rev data sent interrupt. the host timeout interrupt. fdmairq forward transfer dma end of block interrupt rdmairq reverse transfer dma end of block interrupt clearing any interrupt requires writing a 1 to the corresponding bit in the interrupt status register.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 17-11 interrupt mask register address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default parallel port interrupt mask. (pioirqmask) $01ff8211 (not used) dmarirq mask dmafirq mask hte mask rdx mask ivt mask crx mask drx mask rst. value x0000000b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default parallel port interrupt mask (pioirqmask) $01ff8210 inil mask inih mask afdl mask afdh mask strl mask strh mask sinl mask sinh mask rst. value 00h read value 00h the mask register will be used to enable the interrupts when writing one to each corresponding bit and disable the interrupts when writing zero to the corresponding bit. fifo interface register address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default parallel port fifo interface piofifoif 01ff8213 (not used) (not used) revfifo_ lclcleari ng (rd) revfifo_ lclflushi ng (rd) revfifo_ lclreq (rd) fwdfifo_ lclcleari ng (rd) fwdfifo_ lclflushi ng (rd) fwdfifo_ lclreq (rd) rst. value xx000000b read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default parallel port fifo interface piofifoif 01ff8212 revfifo_ lclclr fwdfifo_ lclclr fwdfifo_ tc0en fwdfifo_ enable fwdfifo_ flush revfifo_ tc0en revfifo_ enable revfifo_ flush rst. value 00h read value 00h revfifo_flush causes the reverse fifo to execute a flush of its contents. revfifo_enable enables the reverse fifo operation. when false, any pending dma requests are first completed before the reverse fifo becomes disabled. revfifo_tc0en when low it enables the reverse fifo dma operation. fwdfifo_flush causes the forward fifo to execute a flush of its contents. fwdfifo_enable enables the forward fifo operation. when false, any pending dma requests are first completed before the forward fifo becomes disabled. fwdfifo_tc0ena when low it enables the forward fifo dma operation. fwdfifo_lclclr fwd fifo local asynchronous clear except waits for any pending dma requests to finish before reset. revfifo_lclclr rev fifo local asynchronous clear except waits for any pending dma requests to finish before reset. fwdfifo_lclreq fwd fifo local request is similar to dmareq but ignores dmaeq0 input. used for firmware dma as a status signal. fwdfifo_lclflushing high when lclflush is pulsed high and stays high until the fifo is flushed. fwdfifo_lclclearing high when lclclr is pulsed and stays high until the clear can be done(no dmareq). revfifo_lclreq rev fifo local request is similar to dmareq but ignores dmaeq0 input. used for firmware dma as a status signal. revfifo_lclflushing high when lclflush is pulsed high and stays high until the fifo is flushed. revfifo_lclclearing high when lclclr is pulsed and stays high until the clear can be done (no dmareq).
MFC2000 multifunctional peripheral controller 2000 hardware description 17-12 conexant 100723a dma fifo registers there will be two 4 half word fifos used for forward and reverse dma transfers. the fifo locations will be accessed from cpu as well as dma. the address locations for the forward dma fifo will be 01ff8220 to 01ff822f. the address locations for the reverse fifo will be 01ff8230 to 01ff823f. output data fifo halfword[3:0] for the data to the external memory (the forward direction) (for dma channel 11): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: parallel port output data fifo (piooutfifox) data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: parallel port output data fifo (piooutfifox) data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value 00h read value 00h ? address assignment for output fifo halfword[3:0] the input fifo halfword the register name address output fifo halfword 3 piooutfifo3 01ff8227-26 output fifo halfword 2 piooutfifo2 01ff8225-24 output fifo halfword 1 piooutfifo1 01ff8223-22 output fifo halfword 0 piooutfifo0 01ff8221-20 output data fifo holding register for the data to the external memory (the forward direction) (for dma channel 11): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: parallel port output data fifo holding register (pioouthold) $01ff8229 data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value xxh read value xxh address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: parallel port output data fifo holding register (pioouthold) $01ff8228 data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value 00h read value 00h
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 17-13 output data fifo control register for the data to the external memory (the forward direction) (for dma channel 11): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: parallel port output data fifo control register (piooutfifoctrl) $01ff822b fifo enabled (r) data request (r) fifo ready (r) fifo dma threshold fifo output pointer rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: parallel port output data fifo control register (piooutfifoctrl) $01ff822a (not used) holding register full byte present fifo data quantity fifo input pointer rst value x0000000b read value 00h bit 15: this bit indicates that the fifo is active and capable of generating dma requests. this bit generally follows the setting of the lcl_enb input signal except the fifo enabled register bit will remain asserted if the lcl_enb input signal is set to false while the fifo is executing a dma transfer. in this case, the register bit will remain set for the duration of the dma transfer and then become cleared. bit 14: this bit is similar to the dma_req signal except that it is not blocked when dma_tc0 is set. it indicates that the programmed threshold has been met or exceeded and that the fifo requires data transfers either by enabling hardware dma through dma_tc0 or by executing software dma cycles. bit 13: this bit indicates that the fifo can accept data transfers to/from the local logic. this bit is low when the data direction is into the local logic and the fifo is empty or when the data direction is out of the local logic and the fifo is full. bit 12-10: this bit field indicates at which point the fifo should issue a dma request. it is compared with the fifo data quantity bit field to determine when this should occur. legal values are from 1 to 4. a value of zero causes no data transfers to occur. values greater than 4 are treated as 4. bit 9-8: this bit field indicates which byte of the fifo quad halfword structure is the next to be used as output data. bit 7: not used bit 6: this bit indicates that there is a full word in the holding register. bit 5: this bit indicates that there is a single byte in the holding register. bit 4-2: this bit field indicates the number of quad halfwords that contain data. valid values are from 0 to 4. bit 1-0: this bit field indicates which byte of the fifo quad halfword structure is the next to receive input data. note: it is strongly recommended that the fifo be disabled before firmware writes to the fifo control register. the fifo control register contains data that is essential to the fifo?s operation. if this data is changed while the fifo is operating, unpredictable operation will result.
MFC2000 multifunctional peripheral controller 2000 hardware description 17-14 conexant 100723a input data fifo halfword[3:0] for the data from the external memory (the reverse direction) (for dma channel 12): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: parallel port input data fifo (pioinfifox) data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: parallel port input data fifo (pioinfifox) data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value 00h read value 00h ? address assignment for input fifo halfword[3:0] the input fifo halfword the register name address input fifo halfword 3 pioinfifo3 01ff8237-36 input fifo halfword 2 pioinfifo2 01ff8235-34 input fifo halfword 1 pioinfifo1 01ff8233-32 input fifo halfword 0 pioinfifo0 01ff8231-30 input data fifo holding register for the data from the external memory (the reverse direction) (for dma channel 12): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: parallel port input data fifo holding register (pioinhold) $01ff8239 data bit 15 data bit 14 data bit 13 data bit 12 data bit 11 data bit 10 data bit 9 data bit 8 rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: parallel port input data fifo holding register (pioinhold) $01ff8238 data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 rst value 00h read value 00h
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 17-15 input data fifo control register for the data from the external memory (the reverse direction) (for dma channel 12): address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: parallel port input data fifo control register (pioinfifoctrl) $01ff823b fifo enabled (r) data request (r) fifo ready (r) fifo dma threshold fifo output pointer rst value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: parallel port input data fifo control register (pioinfifoctrl) $01ff823a (not used) holding register full byte present fifo data quantity fifo input pointer rst value x0000000b read value 00h bit 15: this bit indicates that the fifo is active and capable of generating dma requests. this bit generally follows the setting of the lcl_enb input signal except the fifo enabled register bit will remain asserted if the lcl_enb input signal is set to false while the fifo is executing a dma transfer. in this case, the register bit will remain set for the duration of the dma transfer and then become cleared. bit 14: this bit is similar to the dma_req signal except that it is not blocked when dma_tc0 is set. it indicates that the programmed threshold has been met or exceeded and that the fifo requires data transfers either by enabling hardware dma through dma_tc0 or by executing software dma cycles. bit 13: this bit indicates that the fifo can accept data transfers to/from the local logic. this bit is low when the data direction is into the local logic and the fifo is empty or when the data direction is out of the local logic and the fifo is full. bit 12-10: this bit field indicates at which point the fifo should issue a dma request. it is compared with the fifo data quantity bit field to determine when this should occur. legal values are from 1 to 4. a value of zero causes no data transfers to occur. values greater than 4 are treated as 4. bit 9-8: this bit field indicates which byte of the fifo quad halfword structure is the next to be used as output data. bit 7: not used bit 6: this bit indicates that there is a full word in the holding register. bit 5: this bit indicates that there is a single byte in the holding register. bit 4-2: this bit field indicates the number of quad halfwords that contain data. valid values are from 0 to 4. bit 1-0: this bit field indicates which byte of the fifo quad halfword structure is the next to receive input data. note: it is strongly recommended that the fifo be disabled before firmware writes to the fifo control register. the fifo control register contains data that is essential to the fifo?s operation. if this data is changed while the fifo is operating, unpredictable operation will result.
MFC2000 multifunctional peripheral controller 2000 hardware description 17-16 conexant 100723a 17.5 timing 17.5.1 compatibility timing when this mode of handshaking is enabled, the ppi automatically generates busy upon reception of the leading edge of stroben from the host, and latches the logic levels to the ippid bus and autofdn in the parallel port data register. the ppi then waits for the stroben to de-assert and the parallel port data register to be read. after the later of these events occurs, the ppi asserts ackn for the duration specified in the parallel port ack pulse width register and then de-asserts ackn and busy to conclude the data transfer. when data is latched into the parallel port data register, the ppi controller generates two events: an internal parallel port dma request, and a processor interrupt request. software may alternate between dma and interrupt based data transfers. the dma request remain active until the data is read by either the dma channel, or the processor in response to the interrupt request. if the forward dma fifo has been enabled, the forward dma fifo generates fdmareq after reading the parallel port data register and writing the data to its internal half word quad registers. when the fdmack is generated the dma channel reads the forward fifo internal registers, ackn is pulsed, busy is deserted, and the fdmack is cleared. 17.5.1.1 compatibility mode timing diagram 1. host writes data to the data bus 2. if obusy is not active, the host will assert the istroben low. 3. peripheral will assert obusy high to indicate data transfer cycle. 4. host will set the istroben and at the rising edge, the peripheral will latch the data . 5. peripheral asserts oackn low to acknowledge the transfer and drops the obusy. ippid[7:0] stroben busy ackn latch data request interrupt read data make ack pulse figure 17-2. compatibility mode timing diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 17-17 17.5.2 nibble mode timing the nibble mode is the most common way to get reverse channel from printer or peripheral. this mode is usually combined with the compatibility mode or a proprietary forward channel mode to create a complete bi-direction channel. the nibble mode phase transitions: 1. host signal ability to take data by asserting autofdn low 2. peripheral responses by placing first nibble on status lines(faultn,slctout,pe and busy) 3. peripheral signals valid nibble by asserting ackn low 4. host sets autofdn high to indicate that it has received the nibble and is not ready for another nibble. 5. peripheral set ackn high for the second nibble. autofdn ackn faultn slctout pe busy bits[1:4] bits[5:8] figure 17-3. nibble mode data transfer cycle
MFC2000 multifunctional peripheral controller 2000 hardware description 17-18 conexant 100723a 17.5.3 byte mode timing byte mode is a reverse channel data transfer used to provide data rates into the pc approaching that of compatibility mode. the byte mode signal handshaking is as follows: 1. host signals ability to take data by asserting autofdn low 2. peripheral responds by placing first byte on data lines 3. peripheral signals valid byte by asserting ackn low 4. host sets autofdn high to indicate it has received data 5. peripheral sets ackn high to acknowledge host 6. host pulses stroben as an acknowledge to the peripheral. autofdn ackn stroben oppid[7:0] figure 17-4. byte mode data transfer cycle
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 17-19 17.5.4 ecp mode timing two modes of hardware handshaking are offered for ecp forward transfers. ecp mode hardware handshaking is enabled by setting the mode field in the parallel port control register to 2. the ecp mode hardware handshaking with rle is enabled by setting mode to 3. when either mode is enabled, the ppi automatically responds to stroben (hostclk) by latching the logic levels on the pd bus and autofdn in the parallel data register. when the parallel port data register is read, the ppi drives busy high,waits for stroben to high, and then drives busy (periphack) low to conclude the cycle. the busy signal is controlled by the ppi automatically if the data is received using dma mode. note that since no ackn pulse is generated, the pulse width duration specified in the parallel port ack pulse width register is not used in any manner. as in the compatibility handshake mode, data is latched at the leading edge of stroben. this then causes a dma request and posting of drx (data received) interrupt event. dma and interrupt operation is the same as explained in the compatibility mode. in mode 2, reception of both run-length counts and channel addresses causes a crx interrupt event to be posted. software is responsible for responding to channel addresses and performing data decompression. when mode is set to 3, ecp mode hardware handshaking is enabled during forward data transfers, with run length encoding(rle) data compression support. if mode is reprogrammed when decompression is taking place, that is, when rld is set, the decompression continues unhindered to completion. 17.5.4.1 forward ecp transfer handshake: the host places data on the data lines and indicates a data cycle by setting autofdn high. 1. host asserts stroben low to indicate valid data. 2. peripheral acknowledges host by setting busy high. 3. host sets stroben high and the data is clocked in to the peripheral. 4. peripheral sets busy low to indicate that it is ready for the next byte. 5. the cycle repeats, but this time it is a command cycle because autofdn is low. data stroben busy latch data request interrupt read data figure 17-5. ecp mode timing diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 17-20 conexant 100723a 17.5.4.2 reverse ecp transfer handshake 1. the host requests a reverse channel transfer by setting initn low. 2. the peripheral signals that it is ok to proceed by setting pe low. 3. the peripheral places data on the data lines and indicates a data cycle by setting busy high. 4. the peripheral asserts ackn low to indicate valid data. 5. the host acknowledges by setting autofdn high. 6. the peripheral sets ackn high to clock the data in to the host. 7. the host sets autofdn low to indicate that it is ready for the next byte. 8. the cycle repeats, but this time it is a command cycle because ackn is low. initn pe oppid[7:0] data ackn autofdn busy figure 17-6. reverse ecp transfer timing
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 17-21 17.5.5 error cycle timing error cycles are performed by a printer to alert the host of a change in the operational status of the printer. error cycles include such events as the user taking the printer off-line, the occurrence of a paper jam, or the printer running out of paper. an error cycle consists of raising busy, and then changing the state of any one or more of the three status lines, slctout, pe and faultn to reflect the error condition. the errc bit in the control register prevents handshake logic from generating ackn and busy in the compatibility mode. errc slctout pe faultn busy ackn figure 17-7. error cycle timing diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 17-22 conexant 100723a 17.6 firmware operation all the parallel port negotiations will be done in firmware. 17.6.1 disabling all hardware handshaking when hardware handshaking is disabled(mode=0), software is then responsible for controlling the parallel port interface. software can control all parallel port operations including negotiation and termination phases, as well as reverse channel transfers. this provides flexibility to adapt to existing protocols as they are revised and to new protocols as they are created. software can control the busy and ackn interface pins with the fbsy (force busy) and fack (force ackn) bits in the parallel port interface register. the fbsy bit is or?ed with the busy output from the ppi state machine before driving the busy interface pin, and the fack bit is nor?ed with the ackn output from the ppi state machine before driving the ackn interface pin. normally the ppi state machine should be idle when using fbsy and fack. even with all hardware handshaking disabled, the parallel port register continues to latch parallel port data on the leading edge of the stroben. software can issue a rst in the parallel port control register to immediately force the ppi state machine to idle. 17.6.2 software interrupts the following is a list of p1284 signal transition interrupts provided for ease of use: slctinn rising and falling stroben rising and falling (remains high until data is fetched from ppi) initn rising and falling autofdn rising and falling drx data received crx command received ivt invalid transition rdx reverse data transmitted hte host time-out error 17.6.3 interrupt operation there will be a bit corresponding to each interrupt in the interrupt enable register that enables the interrupt. when the event corresponding to an interrupt occurs, this bit needs to be set at the following rising edge of the siu clock. the ppi interface possesses 15 sources of interrupts. each source can post an event in the interrupt status register and each event can be individually enabled or disabled in the interrupt mask register. the fifteen interrupts have been in section 17. the first eight interrupt events signal level changes that occur at the host control signal input pins. note that these events are detected after the host inputs are synchronized, digitally filtered, and recorded in the parallel port interface register.
multifunctional peripheral controller 2000 MFC2000 100723a conexant 18-1 18. real-time clock 18.1 description the real-time clock (rtc) circuit is required to maintain current time information under MFC2000 primary power and battery backup conditions. the rtc circuit consists of six binary counters that track seconds, minutes, hours, days, months, and years elapsed since the reference year, 1992. each counter can be read from the appropriate register described. the tracking range of the rtc is up to 32 years, and automatic compensation is made for leap years. a 32768 hz signal is required to operate rtc counters and logic. a 32768 hz (watch) crystal should be used. the rtc block diagram is illustrated in figure 18-1. 15 bit prescaler 6 bit seconds 6 bit minutes 5 bit hours 1 hz co=60 co=60 co=24 32768 hz busy detect busy flag clear 5 b it days 4 bit months 5 bit years co=28,29, 30, or 30 co=12 month decoder leap year decoder 3 state driver busy flag figure 18-1. rtc block diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 18-2 conexant 100723a 18.2 real-time clock (rtc) registers note: all rtc registers are cleared only by battery power-on reset or a write to the rtc control register. as you can see, second and minute are in the same 16-bit register. hour_day, and month_year registers have the same arrangement. if cpu does a 16-bit write to the hour_day register, both hour and day will increment. if cpu only writes to the lower 8-bit or the upper 8-bit, only hour or only day will increment. the month_year register operates in the same manner. the sec_min register operates differently. if cpu does a 16-bit write or a lower 8-bit write to the sec_min register, year, month, day, hour, and minute will increment once. if cpu only writes to the upper 8-bit, only minute will increment. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: second and minute (sec_min) 01ff8091 busy flag (r) (not used) read: data range 000000 - 111011 write: increment minute, (data is a don?t care) rst. value 0x000000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: second and minute (sec_min) 01ff8090 busy flag (r) (not used) read: data range 000000 - 111011 write: increment all - year,month,day,hour and minute registers, (data is a don?t care) rst. value 0x000000b read value 00h increment all will increment the year, month, day, hour, and minute registers by one. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: hour and day (hour_day) 01ff8093 busy flag (r) (not used) (not used) read: data range 00000 - 11110 write: increment day (data is a don?t care) rst. value 0xx00000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: hour and day (hour_day) 01ff8092 busy flag (r) (not used) (not used) read: data range 00000 - 10111 write: increment hour (data is a don?t care) rst. value 0xx00000b read value 00h address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: month and year (month_year) 01ff8095 busy flag (r) (not used) (not used) read: data range 00000 - 11111 write: increment year (data is a don?t care) rst. value 0xx00000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: month and year (month_year) 01ff8094 busy flag (r) (not used) (not used) (not used) read: data range 0000 - 1011 write: increment month, (data is a don?t care) rst.value 0xxx0000b read value 00h
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 18-3 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: real time clock ctrl (rtc) 01ff8097 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: real time clock ctrl (rtc) 01ff8096 read: clears the busy flag (data is undefined) write: resets the real time clock (rtc), (data is a don't care) rst. value xxh read value 00h read: clear busy flag, data is undefined. write: reset the rtc, data is 'don't care'. 18.3 rtc operations 18.3.1 power-up/power-down operation when prime power is applied to the mfpc and battery reset (batrstn) is generated, all counters in the rtc are reset to 0 and the rtc becomes accessible after a delay of from 125 to 250 ms, provided that the crystal clock is running. (note: the rtc is also software resetable.) when prime power drops below a level where the power-down input (pwrdwnn) becomes active, an internal lockout signal prevents read and write access of the rtc, and rtc operation switches to battery power. inactivation of the pwrdwnn pin (when prime power is restored) removes the lockout condition, and the rtc is again accessible. (note: activation of external reset, resetn, does not affect rtc operation.) 18.3.2 setting time the first step in setting the time is to reset the time counters by writing to the rtc control register. the user can then set the current year (number of years elapsed since the reference year, 1992) into the upper 8- bit of the month_year register. each write to the year register increments the year counter by one. the month is then set by writing to the lower 8-bit of the month_year register, and each write increments the month counter by one. the same procedure should then be used to set the correct day, hour, and minute by writing to the corresponding registers. writing to month_year, hour_day, or sec_min register resets the seconds counter to all zeros. note that the rtc updates the second counter once per second independent of read or write operations to rtc registers. 18.3.3 reading time each 8-bit (upper or lower) of the time interval registers can be independently read. the upper most bit of each 8- bit section is a busy flag, which when set, indicates that a one second clock edge has occurred, and that the time is being updated in all registers. if the busy flag is set when reading any of the time registers, the user must issue a read to the rtc control register to clear the busy flag, and then re-read all of the time registers until all busy flags are 0.
MFC2000 multifunctional peripheral controller 2000 hardware description 18-4 conexant 100723a 18.3.4 crystal oscillator specifications for the clock crystal, a crystal oscillator schematic and circuit board layout recommendations follow. 18.3.5 rtc crystal specifications table 18-1. rtc crystal specifications for 32.768 khz characteristic value for 32.768 khz nominal frequency @25c (f) 32.768 khz 20 ppm turnover temperature (to) 25c 5c temperature characteristic (k)* -0.038 ppm/c2 typ temperature stability -160 ppm, typ @ -40c -137 ppm, typ @ +85c quality factor 100,000 typ load capacitance 12.5 pf 2% series resistance 30 k ? max motional capacitance 3.5 pf typ shunt capacitance 1.7 pf typ maximum drive level 1.0 w aging ( ? f/f) 5.0 ppm, first year operating temperature -10c to +60c *( ? f/f) = k(to-t)2 where t= point of temperature comparison recommended rtc crystal interface circuit typical values fc 32.768 khz r1 10 m ? r2 0 k ? c1 22 pf c2 22 pf amfpc xin xout r1 r2 fc c1 c2 note: adjustment to the values of c1 and c2 may be required to obtain the correct operating frequency due to stray capacitance on the developer?s circuit board.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 18-5 circuit layout criteria for best performance the following design steps should be followed: 1. keep stray capacitance and resistance to a minimum. 2. run xin and xout traces as far apart as possible. 3. clear the ground plane from under the interface circuit. 4. keep digital signals away from this interface. 5. this is a high impedance circuit; residual contamination (e.g., water soluble flux) of this circuit may cause unreliable operation.
MFC2000 multifunctional peripheral controller 2000 hardware description 18-6 conexant 100723a this page is intentionally blank.
multifunctional peripheral controller 2000 MFC2000 100723a conexant 19-1 19. synchronous serial interface (ssif) 19.1 introduction and features 19.1.1 introduction there are two identical ssifs in the MFC2000. the common signal and block names are used in the functional and timing descriptions without indicating which ssif. two ssifs are distinguished as ssif1 and ssif2 only in the register description. the ssif built into the MFC2000, allows system peripherals to communicate with the MFC2000. the ssif provides separate signals for data (sstxd, ssrxd), clock (ssclk), and optional (ssreq) and data acknowledge (ssack). the ssif may be configured to operate as either a master or slave interface. after reset, sstxd is 0 and ssstat is 1. the following describes the operation of this synchronous only serial interface. 19.1.2 features ? full duplex, three wire system ? master or slave operation (bi-directional clock) ? programmable bit rates with maximum frequency = auxclk/ 2 and minimum = auxclk /32 with a 50% duty cycle. ? programmable clock polarity and phase ? internal interrupt for receive register full (mask-able at the interrupt controller) ? optional data request/acknowledge interface during slave mode ? 8 data bit synchronous serial-interface with programmable data shifting order serial in serial out div 8 counter control register clock driver & control carry cnt = 8, irq auxclk ssclk sstxd ssrxd sssta t ir q s sif data bus rd/wr read rst write addr cs serl clk ack latch clr set wr & slave mode serial clk devider 5 bit figure 19-1. ssif block diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 19-2 conexant 100723a 19.2 register description 19.2.1 the 1 st ssif (ssif1) address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: ssdata1 01ff8103 (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: ssdata1 01ff8102 ssdata1 (7-0) rst. value xxh read value xxh register description : ssif1 data register note: the ssdata1 register serves as transmit shift register (txbuffer1) during cpu write, or as receive shift register (rxbuffer1) during cpu read. reading the ssdata1 register will clear the ssinfull1 interrupt bit. writing to the ssdata1 register will reset the shift bit counter, overwrite the output register and initiate an 8 bit serial shift while in serial mode. a bit called ssstatout1 is added into the sscmd1 register. the ssstatout1 value will be output to the ssstat1/gpio[8] pin as the gpio[8] data when the ssstat1/gpio[8] pin is programmed as gpio[8] through the gpioconfig register. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: sscmd1 01ff8101 (not used) (not used) (not used) (not used) (not used) (not used) (not used) ssstatout 1 rst. value xxxxxxx0b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: sscmd1 01ff8100 (not used) (not used) (not used) l2msb1 ssclkpol1 ssclkphas 1 (not used) mode11 0 - master 1 - slave rst. value xxx000x0b read value 00h register description : ssif1 command register bit 8: the ssstatout1 bit is used only when the ssstat1/gpio[8] pin is programmed as gpio[8] through the gpioconfig register. the data value in the ssstatout1 bit is the gpio[8] data value. bit 4: l2msb1, read/write bit. this bit controls the shifting order of the transmit and receive registers. when the l2msb1 bit is cleared (default), the transmit and receive shift register will shift from the msb to the lsb. when the l2msb1 bit is set, the transmit and receive register will shift from the lsb to msb.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 19-3 bit 3: ssclkpol 1, read/write bit. this bit controls the polarity of the ssclk1 pin. the default value is zero. when the ssmode1 is configured at the iomode1, the ssclkpol1 bit will not affect the ssclk1 pin value. bit 2: ssclkphas1, read/write bit. the default value is zero. ssclkpol1 ssclkphas1 description (used for both master and slave modes) 00 enable the external logic to clock the sstxd1 pin on the rising edge of the ssclk1 pin. the ssclk1 pin?s first transition will be in the middle of the first bit. 0 1 enable the external logic to clock the sstxd1 pin on the falling edge of the ssclk1 pin. the ssclk1 pin?s first transition will occur at the beginning of the first bit. 1 0 enable the external logic to clock the sstxd1 pin on the falling edge of the ssclk1 pin. the ssclk1 pin?s first transition will be in the middle of the first bit. 1 1 enable the external logic to clock the sstxd1 pin on the rising edge of the ssclk1 pin. the ssclk1 pin?s first transition will occur at the beginning of the first bit. msb 6 5 4 3 2 1 lsb ssclk1 (ssclkpol1=0, ssclkphas1=0) ssclk1 (ssclkpol1=0, ssclkphas1=1) ssclk1 (ssclkpol1=1, ssclkphas1=0) ssclk1 (ssclkpol1=1, ssclkphas1=1) sstxd1 internal strobe for data capture(all modes) figure 19-2. ssclk1 diagram note : ssclk1 is used to synchronize the movement of data both in and out of device through ssrxd1 and sstxd1 pins. the master and slave devices are capable of exchanging a data byte of information during a sequence of eight clock pulses. both master and slave devices must be operated in the same timing mode as controlled by ssclkpol1 and ssclkphas1 signals. bit 0: mode11, read/write bit. this bit controls the ssif1 master/slave modes. 0: master (default) 1: slave when in the master mode, the ssclk1 pin is configured as an output pin. when in the slave mode, ssclk1 signal is an input to the ssif1.
MFC2000 multifunctional peripheral controller 2000 hardware description 19-4 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: ssdiv1 01ff8105 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: ssdiv1 01ff8104 ssinfull1 (not used) (not used) (not used) ssclk1 divisor rst. value 0xxx0000b read value 00h register description : this register controls the bits of the ssclk1 divisor. bit 7: ssinfull1, read bit. this bit indicates the status of the input register. 0: empty (default) 1: full this bit allows the firmware to poll the status of the serial interface when the use of the interrupt is not desired and is cleared by reading the in ssif1 data register. ssinfull1 is active on the falling edge of auxclk1 and is used by interrupt controller where it masked. bit 6-4: not used bit 3-0: divreg (divisor register), read/write bits. the div register is the ssclk1 divisor register, which defines the ssclk1 frequency. writing the divreg register will cause the ssif1 logic to load the internal counter. firmware can transmit data with the right speed immediately after the ssclk1 setup. the ssclk1 divisor register defines the ssclk1 frequency, which depends on the auxclk frequency. the ssclk1 divisor register is a five bit register. the ssclk1 frequency (f sck )and divisor relationship is: f auxclk divisor sck = + 21 *( )
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 19-5 19.2.2 the 2nd ssif (ssif2) address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: ssdata2 01ff810b (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: ssdata2 01ff810a ssdata2 (7-0) rst. value xxh read value xxh register description : ssif2 data register note: the ssdata2 register serves as transmit shift register (txbuffer2) during cpu write, or as receive shift register (rxbuffer2) during cpu read. reading the ssdata2 register will clear the ssinfull2 interrupt bit. writing to the ssdata2 register will reset the shift bit counter, overwrite the output register and initiate an 8 bit serial shift while in serial mode. a bit called ssstatout2 is added into the sscmd2 register. the ssstatout2 value will be output to the ssstat2/ao[2]/gpo[15] pin as the gpo[15] data when the ssstat2/gpo[15] pin is programmed as gpo[15]. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: sscmd2 01ff8109 (not used) (not used) (not used) (not used) (not used) (not used) (not used) ssstatout 2 rst. value xxxxxxx0b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: sscmd2 01ff8108 (not used) (not used) (not used) l2msb2 ssclkpol2 ssclkphas 2 (not used) mode12 0 - master 1 - slave rst. value xxx000x0b read value 00h register description : ssif2 command register bit 8: the ssstatout2 bit is used only when the ssstat2/ao[2]/gpo[15] pin is programmed as gpo[15]. the data value in the ssstatout2 bit is the gpo[15] data value. bit 4: l2msb2, read/write bit. this bit controls the shifting order of the transmit and receive registers. when the l2msb2 bit is cleared (default), the transmit and receive shift register will shift from the msb to the lsb. when the l2msb2 bit is set, the transmit and receive register will shift from the lsb to msb. bit 3: ssclkpol2, read/write bit. this bit controls the polarity of the ssclk2 pin. the default value is zero. when the ssmode2 is configured at the iomode2, the ssclkpol2 bit will not affect the ssclk2 pin value. bit 2: ssclkphas2, read/write bit. the default value is zero.
MFC2000 multifunctional peripheral controller 2000 hardware description 19-6 conexant 100723a ssclkpol2 ssclkphas2 description (used for both master and slave modes) 0 0 enable the external logic to clock the sstxd2 pin on the rising edge of the ssclk2 pin. the ssclk2 pin?s first transition will be in the middle of the first bit. 0 1 enable the external logic to clock the sstxd2 pin on the falling edge of the ssclk2 pin. the ssclk2 pin?s first transition will occur at the beginning of the first bit. 10 enable the external logic to clock the sstxd2 pin on the falling edge of the ssclk2 pin. the ssclk2 pin?s first transition will be in the middle of the first bit. 1 1 enable the external logic to clock the sstxd2 pin on the rising edge of the ssclk2 pin. the ssclk2 pin?s first transition will occur at the beginning of the first bit. msb 6 5 4 3 2 1 lsb ssclk2 (ssclkpol2=0, ssclkphas2=0) ssclk2 (ssclkpol2=0, ssclkphas2=1) ssclk2 (ssclkpol2=1, ssclkphas2=0) ssclk2 (ssclkpol2=1, ssclkphas2=1) sstxd2 internal strobe for data capture(all modes) figure 19-3. ssclk2 diagram note : ssclk2 is used to synchronize the movement of data both in and out of device through ssrxd2 and sstxd2 pins. the master and slave devices are capable of exchanging a data byte of information during a sequence of eight clock pulses. both master and slave devices must be operated in the same timing mode as controlled by ssclkpol2 and ssclkphas2 signals. bit 0: mode12, read/write bit. this bit controls the ssif2 master/slave modes. 0: master (default) 1: slave when in the master mode, the ssclk2 pin is configured as an output pin. when in the slave mode, ssclk2 signal is an input to the ssif2.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 19-7 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: ssdiv2 01ff810d (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: ssdiv2 01ff810c ssinfull2 (not used) (not used) (not used) ssclk2 divisor rst. value 0xxx0000b read value 00h register description : this register controls the bits of the ssclk2 divisor. bit 7: ssinfull2, read bit. this bit indicates the status of the input register. 0: empty (default) 1: full this bit allows the firmware to poll the status of the serial interface when the use of the interrupt is not desired and is cleared by reading the in ssif2 data register. ssinfull2 is active on the falling edge of auxclk and is used by interrupt controller where it masked. bit 6-4: not used bit 3-0: divreg (divisor register), read/write bits. the div register is the ssclk2 divisor register, which defines the ssclk frequency. writing the divreg register will cause the ssif logic to load the internal counter. firmware can transmit data with the right speed immediately after the ssclk2 setup. the ssclk2 divisor register defines the ssclk2 frequency, which depends on the auxclk frequency. the ssclk2 divisor register is a 5-bit register. the ssclk2 frequency (f sck )and divisor relationship is: to be added 19.3 ssif timing 19.3.1 ssclk timing when ssclk is on (figure 19-4), the duty cycle of ssclk is always 50%. the ssclk polarity is controlled by the ssif command register ssclkpol bit. when the ssclkpol bit and the phase control is cleared (default), the sstxd signal transition is on the ssclk falling edge. external logic can latch the sstxd signal on the ssclk rising edge. when the ssclkpol bit is set, the sstxd signal transition is on the rising edge of the ssclk. external logic can latch the sstxd signal on the ssclk falling edge. for each write to the empty ssif data register, the ssclk will be active for eight cycles. when there is no data on the sstxd pin, the ssclk will stay in idle state, (logic zero when ssclkpol bit is clear, and logic one when the ssclkpol bit is set).
MFC2000 multifunctional peripheral controller 2000 hardware description 19-8 conexant 100723a 19.3.2 request/acknowledge timing request/acknowledge handshaking may be used while the ssif is operating in the slave mode. while in this mode the peripheral (master) may initiate a data transfer by driving the ssack signal low. the ssack signal from the external peripheral is connected to any gpio pin (used as gpi). firmware will in turn write sstxd data to the data register. this will cause the ssif hardware to drive the ssreq(ssstat) signal low. once the ssreq is low the peripheral may start the ssclk to transfer the data. upon completion of the 8 bit transfer, the peripheral must drive the ssack high. the ifc will then read the serial data out of the input register which will in turn drive the ssreq high and complete the transfer. if the ifc wishes to initiate a transfer in this mode it must write to the ssif output register which will in turn set the ssreq low. the peripheral must then provide 8 clocks on the ssclk line to receive the data from the MFC2000?s ssif. preipheral initiated transfer 1 7 8 ssackn ssreqn ssclk serial in full read transfer complete 1 write amfpc initiates transfer figure 19-4. timing diagram
multifunctional peripheral controller 2000 MFC2000 100723a conexant 20-1 20. programmable tone generators 20.1 introduction the amfpc provides three programmable clock generator outputs. two of the generators are to be used as tone generators and the third as a bell or ring driver. 20.2 bell/ringer generator the frequency of this bell/ringer generator is programmable, ranging from 500 hz to 15.6 hz. this frequency is derived from the amfpc?s internal 125 s period clock, and it is calculated based on the following formula: outputfrequency s bellperiod = + 1 125 1 16 () , where bellperiod is ranging from 0 to 31. each bell/ringer period is divided into 16 phases, as shown in the following figure. the phase number may be used by the firmware to determine when to turn off bell signal. 0fedcba9876543210f 1 hi-z hi-z hi-z phase: bell mode: ringer mode: modulated b y alttone generator e period 50% x period 50% x period figure 20-1. bell/ringer timing the mode of operation for this bell/ringer generator is selected by ringerenb bit in bellcontrol register. figure 20-2 shows the block diagram of this bell/ringer generator. table 20-1shows the relationship between bellperiod value and output frequency.
MFC2000 multifunctional peripheral controller 2000 hardware description 20-2 conexant 100723a address decoder bell phase logic a[3:0] cs,r/w 12 5 sclk resn bellperiod reg d[3:0] d[4:0] bellctrl reg d[3:0] alttone fr om a l t t on eg en a l t t o n e e n b to alttonegen bell/ringer figure 20-2. bell/ringer block diagram table 20-1. bell/ringer setting bellperiod+1 bell/ringer freq(hz) bellperiod+1 bell/ringer freq(hz) 1 500 17 29.4 2 250 18 27.8 3 166.7 19 26.3 4 125 20 25 5 100 21 23.8 6 83.3 22 22.7 7 71.4 23 21.7 8 62.5 24 20.8 9 55.6 25 20 10 50 26 19.2 11 45.5 27 18.5 12 41.7 28 17.9 13 38.5 29 17.2 14 35.7 30 16.7 15 33.3 31 16.1 16 31.2 32 15.6
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 20-3 20.2.1 bell mode firmware operation the firmware needs to control bell/ringer generator to issue the following waveform: bell quiet ~ 1s ~ 2s ~ 1s ... ... hi-z hi-z bell in order to setup for bell mode, the following steps must be taken. initialize: 1. write the desired frequency of bell in bellperiod register (see table 20-1) 2. allow hi-z on output (belldriveenb = 0) 3. disable ringer mode (ringerenb = 0) start bell signal: 1. enable bell generator (bellenb = 1) 2. (this setting will start the counter to run) create ?bell-quiet-bell? signal: 1. once the bell signal has been generated, the firmware will read bellperiod register. on every phase a or 9, the off-hook signal is checked. if it is detected, then the bell signal is disabled by having bellenb = 0. this will ensure the bell signal is terminated on the high to high-z transition. 2. if after about 1s, the off-hook signal is not detected, then the firmware will disable the bell signal by having bellenb = 0 when the phase is on 9. when bellenb is reset to 0, then the bell signal will stop at the hi-z, and the phase will be in zero. after about 2 s of quiet, the bell signal can be activated again by setting bellenb to 1. 20.2.2 ringer mode the ringer mode of operation requires the use of both the bell/ringer generator as well as the alttone generator. the fundamental frequency of this ringer signal is the same as the bell signal. the ringer signal works in conjunction with the alttone generator to modulated it?s output. the active window for the ring pulses (bell period high), will automatically shift so that the modulating waveform is not truncated at the beginning or end. note: the firmware needs to control bell/ringer generator to issue the following waveformn: ring quiet ~ 1s ~ 2s ~ 1s ring ... ... figure 20-3. bell/ringer generator waveform
MFC2000 multifunctional peripheral controller 2000 hardware description 20-4 conexant 100723a to setup for ringer mode, the following steps must be taken: initialize : 1. write the desired frequency of bell in bellperiod register (see table 20-1) 2. enable output drive (belldriveenb = 1, will over-ride hi z control) 3. enable ringer mode (ringerenb = 1) 4. write the desired frequency of tone1 in alttonegen register 5. if alttone signal is not desired on the alttone pin, then disable alttone signal to the pin (alttoneenb = 0). note: alttoneenb is only to enable the alttone signal to the alttone pin. if alttoneenb = 0, alttone signal will be blocked to alttone pin, but alttone signal is still available to bell/ringer generator for modulation purpose. start ringer signal: 1. enable bell generator (bellenb = 1) 2. (this setting will start the counter to run) create ?ring-quiet-ring? signal: 1. the firmware can generate the signal by switching the bellenb setting. 20.2.3 registers description the following is a description of the registers used to control the bell/ringer function. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: bellperiod 01ff80b7 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: bellperiod 01ff80b6 (not used) (not used) (not used) bell period (0 - 31), bell period = (bellperiod+1)*2ms rst. value xxx00000b read value 00h register description : bell period register bit 15-5: not used bit 4-0: writing to this register will set the bell period. reading this register will return that value.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 20-5 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: bellphase 01ff80b9 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: bellphase 01ff80b8 (r ) (not used) (not used) (not used) (not used) bell phase rst. value xxxx0000b read value 00h register description : bell phase register bit 15-4: not used bit 3-0: read only register returns current phase of the bell signal. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: bellctrl 01ff80b5 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: bellctrl 01ff80b4 (not used) (not used) (not used) (not used) modtoneen b 1 = enabled ringerenb 1=ring mode 0=bell mode belldrvenb 1 = enabled 0 = allow hi z out bellenb 1 = enabled rst. value xxxx0000b read value 00h register description : bell control register bit 15-4: not used bit 3: enables the alttone output to external pin but has no effect on the ringer mode. if this signal is set to 0 the alttone output will be at 0. bit 2: sets the generator into bell mode or ringer mode (ringer mode overrides bit 1 and does not allow the tristate condition.) bit 1: in bell mode, it controls weighter the output pin is always driven or tristated during bell phases 0, f, 8, and 7. bit 0: enables the bell/ringer counters to run. when this bit is set to 0, the counters are held at the start of phase ?f?. note: after reset the bell/ringer pin will be tristated with the counters held at bell phase ?0?.
MFC2000 multifunctional peripheral controller 2000 hardware description 20-6 conexant 100723a 20.3 tone generator there are two tone generators which can be operated independently, namely alttone and tone. alttone can be used alone or with the bell/ringer generator for modulation purpose. the duty cycle of the tone signal is 50%. frequency modulation on the tone signal can be controlled by the firmware. while the tone generator is running, the firmware may write a new value to the frequency register which will take effect on the start of the next tone cycle. the tone signal is guaranteed to have a smooth transition to the new frequency figure 20-4 shows an example of increasing frequency with smooth transition on the tone signal. glitch free tone: 1 255 counter output: writing a new value to tonegen register figure 20-4. tone generator frequency change 20.3.1 tone/alttone the signal generator called tone, has the ability to generate a dual-tone output. the output frequency switch time and total cycle time are both programmable from 0 to 104.8ms with a step resolution of 102.4us. figure 1-5 is a block diagram of the tone signal generator. frequency register 1 and 2 hold the value of the two alternating frequencies. switch time specifies the time at which the output frequency stitches from freq1 to freq2. the total time register sets the total time of the repeating pattern. figure 1-6 shows the timing diagram of when the output frequency counter switches between freq1 and freq2. figure 1-7 depicts a waveform of a dual-tone output pattern showing what settings effect what portion of the output. figure 1-8 is a block diagram of the alttone frequency generator. frequency register1 10 bits frequency register 2 10 bits tot time cnter 0 - 104.8ms 10 bits sw time cnter 0 - 104.8ms 10 bits select freq out reset psf div 8 pst div 16 iclk/8 6.4us 102.4us 10 total time register switch time register frequency counter 10 bits div 2 carry out ipb_di figure 20-5. dual-tone tone generator block diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 20-7 dual-tone out counter load counter use freq 2 figure 20-6. dual-tone tone generator counter operation frequency 1 frequency 2 switch time total time figure 20-7. dual-tone tone generator output psf div 8 alttone frequency from bellctrl register alttone enb to bell/ringer generator alttone iclk/8 figure 20-8. alttone generator block diagram
MFC2000 multifunctional peripheral controller 2000 hardware description 20-8 conexant 100723a the frequency of the tone generators can be set according to the following formula: tonefrequency auxclk tonegenvalue = ()*** 882 note: tonegenvalue is the value in alttonegen or tonegen freq1 and freq2 registers. when tonegenvalue is zero, then the tone generator is disabled, and the output is low. 20.3.2 registers description address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: alttonegen 01ff80b3 (not used) (not used) (not used) (not used) (not used) (not used) alttone frequency register rst. value xxxxxx00b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: alttonegen 01ff80b2 alttone frequency register rst. value 00h read value 00h register description : alttone generator register. read/write register sets the frequency of modtone. bit 9-0: alttone frequency note: when alttonegen = 0, then alttone is disabled and the alttone output to pin is 0. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: tonegenf1 01ff80b1 (not used) (not used) (not used) (not used) (not used) (not used) tone frequency 1 register rst. value xxxxxx00b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: tonegenf1 01ff80b0 tone frequency 1 register rst. value 00h read value 00h register description : tone generator register. read/write register sets the frequency of tone frequency 1. bit 9-0: tone frequency 1 note: when tone = 0, then tone is disabled and the tone output to pin is 0.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 20-9 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: tonegenf2 01ff80bb (not used) (not used) (not used) (not used) (not used) (not used) tone frequency 2 register rst. value xxxxxx00b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: tonegenf2 01ff80ba tone frequency 2 register rst. value 00h read value 00h register description : tone generator register. read/write register sets the frequency of tone frequency 2. bit 9-0: tone frequency 2 note: when tone = 0, then tone is disabled and the tone output to pin is 0. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: tonegenswitch 01ff80bd (not used) (not used) (not used) (not used) (not used) (not used) tone frequency switch time rst. value xxxxxx00b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: tonegenswitch 01ff80bc tone frequency switch time rst. value 00h read value 00h register description : tone generator frequency switch register. read/write register sets the time of frequency 1 duration. bit 9-0: tone frequency switch time (0 to 104.8 ms in 102.4 us steps) if this register is set to 000h, the output frequency will = freq2 for the total time. if the register value is >= the total time, the output frequency will = freq1 for the total time.
MFC2000 multifunctional peripheral controller 2000 hardware description 20-10 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: tonegentotal 01ff80bf (not used) (not used) (not used) (not used) (not used) (not used) tone frequency total time rst. value xxxxxx00b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: tonegentotal 01ff80be tone frequency total time rst. value 00h read value 00h register description : tone generator total time register. read/write register sets the time of frequency 1 plus frequency 2 duration. when set to 000?h, the tone output will remain low or will be held low once the output switches to it?s low state, and all counters will be held in reset (000?h). when this register is set to a non zero value, the counters will be released alowing generation of the tone signal. the the end of the total time will not take effect until the output of the tone is low, preventing truncation of the ouput signal when high. bit 9-0: tone frequency total time (0 to 104.8 ms in 102.4 us steps)
multifunctional peripheral controller 2000 MFC2000 100723a conexant 21-1 21. pwm logic 21.1 functional description there are five pwm channels, each channel having separate logic and control. pwm channel 0 outputs from the gpio[11]/cpcin pin. there is a pwmch0 select bit in the pwmch0duty register. the pwmch0 select bit goes to the gpio block where the signal selection and the prioritization for the gpio[11]/cpcin/pwm0 pin is done. pwm channel 1 and pwm channel 2 share pins with fcs[0]n and fcs[1]n. there is a pwmch1 select bit in the pwmch1duty register. there is a pwmch2 select bit in the pwmch2duty register. pwm channel 3 shares the pin with gpio[5]/cs[3]n. there is a pwmch3 select bit in the pwmch3duty register. the pwmch3 select bit goes to the gpio block where the signal selection and the prioritization for the gpio[5]/cs[3]n/pwm3 pin is done. pwm channel 4 shares the pin with gpio[10]/p80_pb3. there is a pwmch4 select bit in the pwmch4duty register. the pwmch4 select bit goes to the gpio block. the gpio logic does the signal selection and the prioritization for the gpio[10]/p80_pb3/pwm4 pin. the pwm function requirements are as follows. ? signal frequency range " auxclk/256 or auxclk/(2*256) ? duty cycle " high level: 1/256 to 256/256 ? 8-bit counter for duty cycle programmability
MFC2000 multifunctional peripheral controller 2000 hardware description 21-2 conexant 100723a 21.2 register description name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default pwm channel 0 control (pwmch0ctrl) 01ff80c1h alttone/ pwmch0 output select 0=alttone 1=pwmch0 (not used) (not used) (not used) (not used) (not used) (not used) pwmch0 clock divider rst. value 0xxxxxx0b read value 0xxxxxx0b name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default pwm channel 0 control (pwmch0ctrl) 01ff80c0h bit 7 of pwmch0 duty cycle control bit 6 of pwmch0 duty cycle control bit 5 of pwmch0 duty cycle control bit 4 of pwmch0 duty cycle control bit 3 of pwmch0 duty cycle control bit 2 of pwmch0 duty cycle control bit 1 of pwmch0 duty cycle control bit 0 of pwmch0 duty cycle control rst. value 00h read value 00h bit 15 controls which signal is output to the gpio[11]/cpcin/gpio[11] pin (pwm channel 0 output signal, cpcin input signal, or gpio input/output signal). bit 8/gpioconfig1 register bit 15/pwmch0ctrl register gpio[11]/cpcin/pwm0 pin 0 0 gpio[11] 0 1 gpio[11] 1 0 cpcin 11pwm0 bit 8 pwmch0 clock divider (n = 0-1) pwmch0 clock = auxclk n () + 1 bits 7-0 duty cycle control (n = 0 - 255) pwmch0 signal frequency = pwmch clock 0 256 pwmch0 signal ?high? period = n + 1 256 * pwmch0 signal cycle time pwmch0 signal ?low? period = 256 1 256 ?+ () n * pwmch0 signal cycle time
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 21-3 name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default pwm channel 1 control (pwmch1ctrl) 01ff80c3h pwmch1 output select (not used) (not used) (not used) (not used) (not used) (not used) pwmch1 clock divider rst. value 0xxxxxx0b read value 0xxxxxx0b name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default pwm channel 1 control (pwmch1ctrl) 01ff80c2h bit 7 of pwmch1 duty cycle control bit 6 of pwmch1 duty cycle control bit 5 of pwmch1 duty cycle control bit 4 of pwmch1 duty cycle control bit 3 of pwmch1 duty cycle control bit 2 of pwmch1 duty cycle control bit 1 of pwmch1 duty cycle control bit 0 of pwmch1 duty cycle control rst. value 00h read value 00h bit 15 controls which signal is output to the fcs[0]n pin (pwm channel 1 output signal or the other output signal). bit 8/flashctrl register bit 15/pwmch1ctrl register fcs[0]n/pwm1 pin 00fcs[0] 01fcs[0] 1 0 fcs[0] for nand-type flash mem 11pwm1 bit 8 pwmch1 clock divider (n = 0-1) pwmch1 clock = auxclk n () + 1 bits 7-0 duty cycle control (n = 0 - 255) pwmch1 signal frequency = pwmch clock 1 256 pwmch1 signal ?high? period = n + 1 256 * pwmch1 signal cycle time pwmch1 signal ?low? period = 256 1 256 ?+ () n * pwmch1 signal cycle time
MFC2000 multifunctional peripheral controller 2000 hardware description 21-4 conexant 100723a name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default pwm channel 2 control (pwmch2ctrl) 01ff80c5h pwmch2 output select (not used) (not used) (not used) (not used) (not used) (not used) pwmch2 clock divider rst. value 0xxxxxx0b read value 0xxxxxx0b name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default pwm channel 2 control (pwmch2ctrl) 01ff80c4h bit 7 of pwmch2 duty cycle control bit 6 of pwmch2 duty cycle control bit 5 of pwmch2 duty cycle control bit 4 of pwmch2 duty cycle control bit 3 of pwmch2 duty cycle control bit 2 of pwmch2 duty cycle control bit 1 of pwmch2 duty cycle control bit 0 of pwmch2 duty cycle control rst. value 00h read value 00h bit 15 controls which signal is output to the fcs[1]n pin (pwm channel 2 output signal or the other output signal). bit 9/flashctrl register bit 15/pwmch2ctrl register fcs[1]n/pwm2 pin 00fcs[1] 01fcs[1] 1 0 fcs[1] for nand-type flash mem 11pwm2 bit 8 pwmch2 clock divider (n = 0-1) pwmch2 clock = auxclk n () + 1 bits 7-0 duty cycle control (n = 0 - 255) pwmch2 signal frequency = pwmch clock 2 256 pwmch2 signal ?high? period = n + 1 256 * pwmch2 signal cycle time pwmch2 signal ?low? period = 256 1 256 ?+ () n * pwmch2 signal cycle time
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 21-5 name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default pwm channel 3 control (pwmch3ctrl) 01ff80c7h pwmch3 output select (not used) (not used) (not used) (not used) (not used) (not used) pwmch3 clock divider rst. value 0xxxxxx0b read value 0xxxxxx0b name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default pwm channel 3 control (pwmch3ctrl) 01ff80c6h bit 7 of pwmch3 duty cycle control bit 6 of pwmch3 duty cycle control bit 5 of pwmch3 duty cycle control bit 4 of pwmch3 duty cycle control bit 3 of pwmch3 duty cycle control bit 2 of pwmch3 duty cycle control bit 1 of pwmch3 duty cycle control bit 0 of pwmch3 duty cycle control rst. value 00h read value 00h bit 15 controls which signal is output to the gpio[5] pin (pwm channel 3 output signal or the other output signal). bit 4/gpioconfig1 register bit 15/pwmch3ctrl register gpio[5]/cs[3]n/pwm3 pin 0 0 gpio[5] 0 1 gpio[5] 1 0 cs[3]n 11pwm3 bit 8 pwmch3 clock divider (n = 0-1) pwmch3 clock = auxclk n () + 1 bits 7-0 duty cycle control (n = 0 - 255) pwmch3 signal frequency = pwmch clock 3 256 pwmch3 signal ?high? period = n + 1 256 * pwmch3 signal cycle time pwmch3 signal ?low? period = 256 1 256 ?+ () n * pwmch3 signal cycle time
MFC2000 multifunctional peripheral controller 2000 hardware description 21-6 conexant 100723a name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default pwm channel 4 control (pwmch4ctrl) 01ff80c9h pwmch4 output select (not used) (not used) (not used) (not used) (not used) (not used) pwmch4 clock divider rst. value 0xxxxxx0b read value 0xxxxxx0b name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default pwm channel 4 control (pwmch4ctrl) 01ff80c8h bit 7 of pwmch4 duty cycle control bit 6 of pwmch4 duty cycle control bit 5 of pwmch4 duty cycle control bit 4 of pwmch4 duty cycle control bit 3 of pwmch4 duty cycle control bit 2 of pwmch4 duty cycle control bit 1 of pwmch4 duty cycle control bit 0 of pwmch4 duty cycle control rst. value 00h read value 00h bit 15 controls which signal is output to the gpio[10] pin (pwm channel 4 output signal or the other output signal). bit 7/gpioconfig1 register bit 15/pwmch4ctrl register gpio[10]/p80_pb3/pwm4 pin 0 0 gpio[10] 0 1 gpio[10] 1 0 p80_pb3 11pwm4 bit 8 pwmch4 clock divider (n = 0-1) pwmch4 clock = auxclk n () + 1 bits 7-0 duty cycle control (n = 0 - 255) pwmch4 signal frequency = 256 4 clock pwmch pwmch4 signal ?high? period = n + 1 256 * pwmch4 signal cycle time pwmch4 signal ?low? period = 256 1 256 ?+ () n * pwmch4 signal cycle time
multifunctional peripheral controller 2000 MFC2000 100723a conexant 22-1 22. calling party control (cpc) in some countries, after the called party is on hook, a pulse is sent to the caller party by stopping the line current of the caller party for a short time to indicate that the called party is on hook, as seen in figure 22-1. the duration of this pulse varies widely for different countries. the purpose of having calling party control (cpc) circuit is to detect the on-hook signal by sampling cpc signal. . . (of caller party) caller party c alled p arty line current cpc signal o ff-h ook on-hook on-hook signal o ff-h ook on-hook figure 22-1: cpc signal firmware note : in order to setup cpc circuit, the following initialization procedure must be done in the given order after both parties are off hook: 1. write the desired threshold in cpcthreshold register 2. select the sampling period in cpcstatctrl register (this will clear the cpcflag and reset cpc counter to zero) once cpc has been set up, the firmware can periodically check cpcflag by reading cpcstatctrl register.
MFC2000 multifunctional peripheral controller 2000 hardware description 22-2 conexant 100723a tthe following flowchart illustrates the cpc operation: check cpc signal on every sampling clock cpc signal lev el ? increment counter flag ? is there write signal to cpcstatctrl ? com pare count value with threshold count = threshold ? flag ? flag = high flag = low reset counter figure 22-2. cpc operation flowchart
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 22-3 figure 22-3 illustrates an example of the cpc operation with cpcthreshold containing a value of 4. cpc signal cpc count sampling cpc 0120 12 34 0 counteqthr cpcflag false on-hook signal cpc statctrlw rn cpc statctrlrdn this noise will be filtered out. 1 2 3 4 figure 22-3: cpc operation (with cpcthreshold = 4) note : 1. writing to cpcstatctrl register will clear cpc flag. 2. whenever both cpc signal and cpc flag are low, the counter is reset in order to restart the counting sequence. the previous counter value is regarded as the result from a noise signal. this condition is only checked at every sampling time. in other words, if it happens between the sampling time, then the noise will be filtered out. 3. as soon as the counter value is equal to the threshold value, cpc flag is raised. 4. once cpc flag has been raised, the counter will be clear on the next sampling clock. figure 22-4 illustrates the cpc block diagram.
MFC2000 multifunctional peripheral controller 2000 hardware description 22-4 conexant 100723a cpcthreshold r eg ister address decoder a[3:0] cs,r/w cpcstatctrl r egister 125 sc lk cpcsignal 8-bit counter clock divider comparator control logic cpcstatctrlrdn c pcstatc trlw rn b a a= b figure 22-4: cpc block diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 22-5 22.1 registers description name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default cpc threshold ( cpcthreshold ) 01ff80a9 (not used) rst value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default cpc threshold ( cpcthreshold ) 01ff80a8 cpc threshold rst value ffh read value ffh bit 15?8 not used bit 7?0 cpc threshold name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default cpc status & control ( cpcstatctrl ) 01ff80ab (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default cpc status & control ( cpcstatctrl ) 01ff80aa cpc flag (r) cpc signal (r) (not used) (not used) (not used) (not used) sampling clock select: 0: 125 s 1: 500 s 2: 2 ms 3: 8 ms rst value xxxxxx11b read value 00000011b bit 15?8 not used bit 7 cpc flag bit 6 cpc signal bit 5?2 not used bit 1?0 sampling clock selection
MFC2000 multifunctional peripheral controller 2000 hardware description 22-6 conexant 100723a this page is intentionally blank
multifunctional peripheral controller 2000 MFC2000 100723a conexant 23-1 23. ssd_p80 23.1 function description a 56k/33.6k data/fax modem core is integrated into the MFC2000 chip. it is called the p80 core. furthermore, conexant?s smartdaa technology is put into the MFC2000 chip. the p80 core can be connected to the phone line through either the modem ia/traditional daa or the smartdaa system side device (ssd) logic/the smartdaa line side device (lsd). the ssd logic is integrated into the MFC2000 chip. the ssd_p80 block includes the ssd logic, p80 core, and interface logic to the internal arm bus system. 23.1.1 system configurations the ssd_p80 can be configured in the following ways. ? configuration one: data acquisition is done only via ssd. ? configuration two: data acquisition is done via ssd and voice acquisition is done via external ia. ? configuration three: data acquisition is done only via external ia. configuration one MFC2000 ssd siu interface m_clk ia interface p80 core m_strobe m_txssd m_rxssd lsd_reg. lsd external figure 23-1. system configuration one
MFC2000 multifunctional peripheral controller 2000 hardware description 23-2 conexant 100723a configuration two MFC2000 siu interface ia interface p80 core external external ia ia1clk m_tx m_strobe m_control m_rx iaclk figure 23-2. system configuration two configuration three MFC2000 ssd siu interface m_clk primary ia interface p80 core m_strobe m_txssd m_rxssd lsd_reg. lsd external external ia v_sclk v_txsin v_strobe v_ctrl v_rx secondary ia interface figure 23-3. system configuration three
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 23-3 23.2 register description address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: p80control 0x01ff88e1 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: p80control 0x01ff88e0 (not used) ssd ringwaken ssd raw_ringn ext raw_ringn ring_sel[1:0] extia_ mode ia_sel rst value xxxx0000b read value 00h bit 15:7 not used bit 6 this is read only bit which indicates status of ring envelope from ssd. bit 5 this is a read only bit which indicates raw ring signals from ssd. bit 4 this is a read only bit which indicates raw ring signals from external daa. bit 3:2 this control bits are used to select types of ring signals to be connected to p80_core to perform ring detection. ?00? : no selection, logic ?high? will be driven to pb[3]_c of p80_core. ?01? : ssd raw_ringn is selected. ?10? : ssd ringwaken is selected. ?11? : external daa raw_ringn is selected. bit 1 this bit controls muxing of output i/o pins. when asserted to high, selected p80 core pins will be directed to external pin. bit 0 this bit controls muxing of primary and secondary i/o pins in p80 core. when asserted to high, secondary i/o will be selected.
MFC2000 multifunctional peripheral controller 2000 hardware description 23-4 conexant 100723a 23.2.1 ssd registers note : for detailed desciption on register contents, refer to ssd spec. table 23-1. ssd registers register name mfc2k address bit positions r/w # bits ssd register 00 00c30050 7:0 r/w 8 ssd register 01 00c30052 7:0 r/w 8 ssd register 02 00c30054 7:0 r/w 8 ssd register 03 00c30056 7:0 r/w 8 ssd register 04 00c30058 7:0 r/w 8 ssd register 05 00c3005a 7:0 r/w 8 ssd register 06 00c3005c 7:0 r/w 8 ssd register 07 00c3005e 7:0 r/w 8 ssd register 08 00c30060 7:0 r/w 8 ssd register 09 00c30062 7:0 r/w 8 ssd register 0a 00c30064 7:0 r/w 8 ssd register 0b 00c30066 7:0 r/w 8 ssd register 0c 00c30068 7:0 r/w 8 ssd register 0d 00c3006a 7:0 r/w 8 ssd register 0e 00c3006c 7:0 r/w 8 ssd register 0f 00c3006e 7:0 r/w 8 ssd register 10 00c30070 7:0 r/w 8 ssd register 11 00c30072 7:0 r/w 8 ssd register 12 00c30074 7:0 r/w 8 ssd register 13 00c30076 7:0 r/w 8 ssd register 14 00c30078 7:0 r/w 8 ssd register 15 00c3007a 7:0 r/w 8 ssd register 16 00c3007c 7:0 r/w 8 ssd register 17 00c3007e 7:0 r/w 8 ssd register 18 00c30080 7:0 r/w 8 ssd register 19 00c30082 7:0 r/w 8 ssd register 1a 00c30084 7:0 r/w 8 ssd register 1b 00c30086 7:0 r/w 8 ssd register 1c 00c3008e 7:0 r/w 8
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 23-5 23.2.2 p80 core registers note : for detailed description on register contents, refer to fm336 hardware spec. table 23-2. p80 core registers register name mfc2k address bit positions r/w # bits p80 register 00 00c30000 7:0 r/w 8 p80 register 01 00c30002 7:0 r/w 8 p80 register 02 00c30004 7:0 r/w 8 p80 register 03 00c30006 7:0 r/w 8 p80 register 04 00c30008 7:0 r/w 8 p80 register 05 00c3000a 7:0 r/w 8 p80 register 06 00c3000c 7:0 r/w 8 p80 register 07 00c3000e 7:0 r/w 8 p80 register 08 00c30010 7:0 r/w 8 p80 register 09 00c30012 7:0 r/w 8 p80 register 0a 00c30014 7:0 r/w 8 p80 register 0b 00c30016 7:0 r/w 8 p80 register 0c 00c30018 7:0 r/w 8 p80 register 0d 00c3001a 7:0 r/w 8 p80 register 0e 00c3001c 7:0 r/w 8 p80 register 0f 00c3001e 7:0 r/w 8 p80 register 10 00c30020 7:0 r/w 8 p80 register 11 00c30022 7:0 r/w 8 p80 register 12 00c30024 7:0 r/w 8 p80 register 13 00c30026 7:0 r/w 8 p80 register 14 00c30028 7:0 r/w 8 p80 register 15 00c3002a 7:0 r/w 8 p80 register 16 00c3002c 7:0 r/w 8 p80 register 17 00c3002e 7:0 r/w 8 p80 register 18 00c30030 7:0 r/w 8 p80 register 19 00c30032 7:0 r/w 8 p80 register 1a 00c30034 7:0 r/w 8 p80 register 1b 00c30036 7:0 r/w 8 p80 register 1c 00c30038 7:0 r/w 8 p80 register 1d 00c3003a 7:0 r/w 8 p80 register 1e 00c3003c 7:0 r/w 8 p80 register 1f 00c3003e 7:0 r/w 8
MFC2000 multifunctional peripheral controller 2000 hardware description 23-6 conexant 100723a 23.3 firmware operation note : all ssd and p80 core registers are 8-bit registers.
multifunctional peripheral controller 2000 MFC2000 100723a conexant 24-1 24. countach imaging dsp bus subsystem the countach imaging dsp bus subsystem contains the countach imaging dsp subsystem for video/scan image signal processing and all peripherals/memory needed for the whole operations. the main memory for image data storage is the external dram/sdram. these peripherals are countach subsystem interface, scan ia, video/scan controller, sdram controller, video/scan interface, arm bus interface, cdma controller, and countach bus unit. the countach imaging dsp subsystem should operate at 100 mhz or 85.7mhz. this is the separate bus system from the arm bus system and runs in parallel with the arm bus system to get maximum performance out of the MFC2000. arm bus interface logic is the bridge between the arm bus system and the countach imaging dsp bus subsystem. both cpu access and dma access mastered by the arm side are supported to coordinate the entire system operation. several blocks are used to complete the connection between these peripherals: 1. arm bus interface ? connects the arm subsystem to the internal busses. 2. countach subsystem interface ? connects the countach core to the internal busses. 3. sync. dram controller ? connects the external dram/sdram to the internal busses. 4. video/scan interface ? connects the video/scan controller to the internal busses. several blocks are used for internal functions: 1. countach bus unit ? connects all internal blocks in the countach bus subsystem together. 2. countach dma controller ? paces all dma transaction between the video/scan interface for video capture and scanner, arm bus interface for arm bus system, and the countach subsystem interface for the countach subsystem to and from the sdram. several i/o accesses on the countach bus subsystem are planned: 1. arm accesses the scratch pad of the countach subsystem through arm bus interface, countach bus unit, and countach subsystem if. note : arm will be able to access all registers in the sub-block of the countach bus subsystem through the ipb bus of the arm bus system. the arm must not access the scratchpad while dma to or from the countach imaging dsp subsystem is in progress. failure to do so can result in corruption and/or loss of dma data. the arm may access the scratchpad during all other dma transfers, including video/scanner data to sdram and sdram to and from arm dram. 2. put the dma setting data to the countach dma controller from the scratch pad of the countach subsystem through countach bus unit, and countach subsystem if after the countach bus unit is informed by the gpo signal from countach subsystem. several dma accesses on the countach bus subsystem are planned: 1. the dma operation to send video and scan image data to the external sdram/dram from the video/scan controller through the video/scan interface. 2. the dma operation to send/receive data from/to memory on the arm bus system through arm bus interface. 3. the dma operation to send/receive data from/to the scratch pad of the countach subsystem through countach subsystem interface.
MFC2000 multifunctional peripheral controller 2000 hardware description 24-2 conexant 100723a countach subsystem video capture chip arm bus system (s)dram device video/ scan controller sync. dram controller scan integrated analog arm bus if countach subsystem if video/ scan if countach bus unit scanner video dma controller figure 24-1. the arm bus system block diagram
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-3 24.1 countach imaging dsp subsystem 24.1.1 description the countach imaging dsp subsystem is mainly responsible for monochrome and color image processing and jpeg compression and decompression. the countach imaging dsp subsystem contains the countach core, data ram and rom, program ram and program rom, scratch pad, and dma channels. 24.1.2 countach imaging dsp subsystem memory program memory: ? 2k 40 ram ? rom for program initialization data ram: ? 1k 16 register file ram ? 4k 16 dma-accessible ram ? 4k 16 ram ? 8k x 16 rom 24.1.3 countach imaging dsp subsystem dma data dma: ? 4 channels ? dma accesses are made via the scratch pad interface ? countach imaging dsp controls which bank dma transfers occur in ? dma channel does not automatically switch after completion of a block transfer ? consecutive dma cycles must be able to occur at a minimum rate of 6 countach clocks per transfer program dma: ? minimum of 1 channel ? dma accesses are made via the scratch pad interface ? consecutive dma cycles must be able to occur at a minimum rate of 6 countach clocks per transfer ? an entire instruction is formed by transferring it in three 16-bit segments to scratch pad addresses 0x1b0, 0x1b1, and 0x1b2 24.1.4 running frequency the countach imaging dsp subsystem operates at either 87.5mhz or 100 mhz. it is configurable through the clk_config[2] signal which is muxed on the romcsn pin.
MFC2000 multifunctional peripheral controller 2000 hardware description 24-4 conexant 100723a 24.2 countach imaging dsp bus unit 24.2.1 function description the countach bus unit is the conduit for all data and address between the various block of the countach bus system. it also decides which blocks become master of these busses. there are four busses in the countach bus system: ? cpb ? address and data to and from the countach subsystem interface ? dpb ? address and data to and from the synchronous dram interface ? ipb ? address and data to and from the arm bus interface ? vpb ? data from the video/scan interface because of these separate busses (as opposed to a single tri-state muxed bus), it is possible to have multiple bus masters. the possible connections between these busses are: ? ipb ? cpb, vpb ? dpb: arm bus interface makes discrete i/o accesses to countach subsystem scratch pad while video/scan interface makes dma accesses to synchronous dram interface. ? cpb ? dpb: countach subsystem interface makes dma accesses to synchronous dram interface. ? ipb ? dpb, {countach dma controller} ? cpb: arm bus interface makes either discrete i/o accesses or dma accesses to synchronous dram interface while countach dma controller fetches dma parameters from countach subsystem scratch pad. 24.2.2 register description address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: deferred read high address (defrdhiaddr) $01ff82a9 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: deferred read high address (defrdhiaddr) $01ff82a8 (not used) deferred read address [22] deferred read address [21] deferred read address [20] deferred read address [19] deferred read address [18] deferred read address [17] deferred read address [16] rst value x0000000b read value 00h bit 15-7 not used bit 6-0 deferred read address [22:16] these seven bits, in conjunction with the sixteen bits of the deferred read low address register, make up the deferred read address. it is a halfword address, not a byte address.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-5 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: deferred read low address (defrdloaddr) $01ff82ab deferred read address [15] deferred read address [14] deferred read address [13] deferred read address [12] deferred read address [11] deferred read address [10] deferred read address [9] deferred read address [8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: deferred read low address (defrdloaddr) $01ff82aa deferred read address [7] deferred read address [6] deferred read address [5] deferred read address [4] deferred read address [3] deferred read address [2] deferred read address [1] deferred read address [0] rst value 00h read value 00h bit 15-0 deferred read address [15:0] these sixteen bits, in conjunction with the seven bits of the deferred read high address register, make up the deferred read address. it is a halfword address, not a byte address. notes : 1. the deferred read address is a halfword address in the countach bus subsystem address space. countach dram address space is $000000?$3fffff and countach subsystem scratch pad address space is $400000?$4001ff. 2. writing this register begins the deferred access operation. this register must be the last one written when initiating a deferred read access. 3. during a deferred read access, all deferred registers are locked out from arm writes. 4. when the deferred read access completes, an interrupt is generated via the countach dma done bit in the arm bus interface interrupt status register. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: deferred write high address (defwrhiaddr) $01ff82ad (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: deferred write high address (defwrhiaddr) $01ff82ac (not used) deferred write address [22] deferred write address [21] deferred write address [20] deferred write address [19] deferred write address [18] deferred write address [17] deferred write address [16] rst value x0000000b read value 00h bit 15-7 not used bit 6-0 deferred write address [22:16] these seven bits, in conjunction with the sixteen bits of the deferred write low address register, make up the deferred write address. it is a halfword address, not a byte address.
MFC2000 multifunctional peripheral controller 2000 hardware description 24-6 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: deferred write low address (defwrloaddr) $01ff82af deferred write address [15] deferred write address [14] deferred write address [13] deferred write address [12] deferred write address [11] deferred write address [10] deferred write address [9] deferred write address [8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: deferred write low address (defwrloaddr) $01ff82ae deferred write address [7] deferred write address [6] deferred write address [5] deferred write address [4] deferred write address [3] deferred write address [2] deferred write address [1] deferred write address [0] rst value 00h read value 00h bit 15-0 deferred write address [15:0] these sixteen bits, in conjunction with the seven bits of the deferred write high address register, make up the deferred write address. it is a halfword address, not a byte address. notes : 3. the deferred write address is a halfword address in the countach bus subsystem address space. countach dram address space is $000000?$3fffff and countach subsystem scratch pad address space is $400000?$4001ff. 4. writing this register begins the deferred access operation. this register must be the last one written when initiating a deferred write access. 5. during a deferred write access, all deferred registers are locked out from arm writes. 6. when the deferred write access completes, an interrupt is generated via the countach dma done bit in the arm bus interface interrupt status register. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: deferred read data (r) (defrddata) $01ff82b1 deferred read data [15] (r) deferred read data [14] (r) deferred read data [13] (r) deferred read data [12] (r) deferred read data [11] (r) deferred read data [10] (r) deferred read data [9] (r) deferred read data [8] (r) rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: deferred read data (r) (defrddata) $01ff82b0 deferred read data [7] (r) deferred read data [6] (r) deferred read data [5] (r) deferred read data [4] (r) deferred read data [3] (r) deferred read data [2] (r) deferred read data [1] (r) deferred read data [0] (r) rst value 00h read value 00h bit 15-0 deferred read data this read-only register contains the deferred read data at the completion of a deferred read access operation. its contents are valid when the countach dma done bit in the arm bus interface interrupt status register is set.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-7 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: deferred write data (defwrdata) $01ff82b3 deferred write data [15] deferred write data [14] deferred write data [13] deferred write data [12] deferred write data [11] deferred write data [10] deferred write data [9] deferred write data [8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: deferred write data (defwrdata) $01ff82b2 deferred write data [7] deferred write data [6] deferred write data [5] deferred write data [4] deferred write data [3] deferred write data [2] deferred write data [1] deferred write data [0] rst value 00h read value 00h bit 15-0 deferred write data this register contains the data to be written during a deferred write access operation. notes : this register must be written before beginning the deferred write access via a write to the deferred write low address register. during a deferred write access, all deferred registers are locked out from arm writes.
MFC2000 multifunctional peripheral controller 2000 hardware description 24-8 conexant 100723a 24.3 arm bus interface 24.3.1 function description the arm bus interface block attaches the countach bus subsystem to the arm bus system. the arm can directly access the various registers of the countach bus subsystem. it can access the countach bus subsystem?s sdram and the countach imaging dsp subsystem?s scratch pad memory and the sdram with discrete i/o accesses with some wait state penalty. it can also access the sdram via dma accesses. to accommodate the arm dma interchange, two channels are provided: one for transfers into the sdram and one for transfers out of the sdram. in addition, two handshaking signals are provided for interrupting of each processor and allow the arm to interrupt the countach core. it is implemented through a register in the countach subsystem interface. the arm_attn signal comes directly from the countach core and is an input to the arm interrupt controller. 24.3.2 register description address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: arm bus interface interrupt status (abiirqstat) $01ff8283 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: arm bus interface interrupt status (abiirqstat) $01ff8282 (not used) (not used) countach subsystem interrupt vsi overrrun deferred access done c2a dma done countach dma done video/ scan dma done rst value xx000000b read value 00h bit 15-6 not used bit 5 countach subsystem interrupt countach subsystem has interrupted the arm either in irqp or irqp2, depending on the setting of the countach interrupt source bit of the abicountachctrl register. bit 4 vsi overrun the second vsi ping-pong buffer has been filled before the first has been emptied, resulting in loss of data. bit 3 deferred access done a deferred access to/from scratch pad or sdram has completed. if a deferred read was requested, the data in the deferred read access data register is now valid. bit 2 c2a dma done c2a (sdram to arm bus system) block size has been reached. bit 1 countach dma done dma operation specified by countach scratch pad parameters has completed. bit 0 video/scan dma done two-dimensional dma from video/scan interface to sdram has completed (two fields) or one scan line has completed. note : each of these bits are cleared by writing it to a one. this allows individual interrupts to be cleared without affecting the others.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-9 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: arm bus interface interrupt enable (abiirqenable) $01ff8285 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: arm bus interface interrupt enable (abiirqenable) $01ff8284 (not used) (not used) countach interrupt enable vsi overrrun interrupt enable deferred access interrupt enable c2a dma interrupt enable countach dma interrupt enable video/ scan dma interrupt enable rst value xx000000b read value 00h bit 15-6 not used bit 5 countach interrupt enable enables interrupt when the countach has interrupted the arm bus via the irqp or irqp2 signals. bit 4 vsi overrun interrupt enable enables interrupt when the second vsi ping-pong buffer has been filled before the first has been emptied, indicating in loss of data. bit 3 deferred access interrupt enable enables interrupt when a deferred access to/from scratch pad or sdram has completed. bit 2 c2a dma interrupt enable enables interrupt when c2a (sdram to arm bus system) block size has been reached. bit 1 countach dma interrupt enable enables interrupt when dma operation specified by countach scratch pad parameters has completed. bit 0 video/scan dma interrupt enables interrupt when two-dimensional dma from video/scan interface to sdram has completed (two fields) or one scan line has been completed. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: arm bus interface countach control (w) (abicountachctrl) $01ff8287 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: arm bus interface countach control (w) (abicountachctrl) $01ff8286 (not used) (not used) countach interrupt source reset countach bus subsystem (w) start countach dma (w) abort countach dma (w) reset countach subsystem (w) interrupt countach subsystem (w) rst value xxxx0000b read value 00h bit 15-6 not used bit 5 countach interrupt source this bit selects which interrupt output from the countach dsp subsystem is used to interrupt the arm via the countach interrupt bit in the arm bus interface interrupt status register. a value of 0 selects the irqp signal and a value of 1 selects the irqp2 signal. bit 4 reset countach bus subsystem writing a one to this bit resets the entire countach bus subsystem (cbss.)
MFC2000 multifunctional peripheral controller 2000 hardware description 24-10 conexant 100723a bit 3 start countach dma writing a one to this bit causes the countach dma controller to fetch parameters from scratch pad and begin a dma transfer. bit 2 abort countach dma writing a one to this bit causes any countach dma operation (cdma channel 1) to be aborted. the countach receives the countach dma done interrupt after the dma has aborted (extirq2). bit 1 reset countach subsystem writing a one to this bit resets the countach subsystem and the countach subsystem interface which contains the dma fifos. bit 0 interrupt countach subsystem writing a one to this bit generates an interrupt to the countach subsystem (extirq). 24.3.3 internal memory the arm bus interface contains two 4 16 buffers for dma transfers between memory attached to the arm bus subsystem and the countach sdram. these buffers can be accessed by the arm as either bytes or halfwords. the two buffers are located at the following addresses: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: arm to countach dma buffer (a2cdmabuf) $01ff830x a2c buffer data [15] a2c buffer data [14] a2c buffer data [13] a2c buffer data [12] a2c buffer data [11] a2c buffer data [10] a2c buffer data [9] a2c buffer data [8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: arm to countach dma buffer (a2cdmabuf) $01ff830x a2c buffer data [7] a2c buffer data [6] a2c buffer data [5] a2c buffer data [4] a2c buffer data [3] a2c buffer data [2] a2c buffer data [1] a2c buffer data [0] rst value 00h read value 00h $01ff8300-01 a2c dma buffer halfword 0 $01ff8302-03 a2c dma buffer halfword 1 $01ff8304-05 a2c dma buffer halfword 2 $01ff8306-07 a2c dma buffer halfword 3 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: countach to arm dma buffer (c2admabuf) $01ff830x c2a buffer data [15] c2a buffer data [14] c2a buffer data [13] c2a buffer data [12] c2a buffer data [11] c2a buffer data [10] c2a buffer data [9] c2a buffer data [8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: countach to arm dma buffer (c2admabuf) $01ff830x c2a buffer data [7] c2a buffer data [6] c2a buffer data [5] c2a buffer data [4] c2a buffer data [3] c2a buffer data [2] c2a buffer data [1] c2a buffer data [0] rst value 00h read value 00h $01ff8308-09 c2a dma buffer halfword 0 $01ff830a-0b c2a dma buffer halfword 1 $01ff830c-0d c2a dma buffer halfword 2 $01ff830e-0f c2a dma buffer halfword 3
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-11 arm access to the abi buffers are provided for diagnostic purposes only and should not be used as part of normal operation. when the arm makes an access to these buffers, the arm is held off and clock domain synchronization occurs before the access is completed. as a result, a significant wait state penalty is incurred. this penalty will be even longer if a local dma operation is in progress when the access is made as the arm is held off for both the clock domain synchronization and the completion of the local dma transfer. there is a risk of data corruption when the arm makes write accesses to these buffers while a dma transfer is in progress. this can occur because the buffers alternate betweeen a dma transfer sequence in the arm bus subsystem domain and a dma transfer sequence in the countach bus subsystem domain. if the write operation occurs between these dma transfers, the dma data in the buffer will be replaced with the arm data. 24.4 countach imaging dsp subsystem interface arm as either bytes or halfwords. the buffer is located at the following addresses: address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: countach dma buffer (csidmabuf) $01ff830x csi buffer data [15] csi buffer data [14] csi buffer data [13] csi buffer data [12] csi buffer data [11] csi buffer data [10] csi buffer data [9] csi buffer data [8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: countach dma buffer (csidmabuf) $01ff830x csi buffer data [7] csi buffer data [6] csi buffer data [5] csi buffer data [4] csi buffer data [3] csi buffer data [2] csi buffer data [1] csi buffer data [0] rst value 00h read value 00h table 24-1. needs a title $01ff8300-01 csi dma buffer halfword 0 $01ff8302-03 csi dma buffer halfword 1 $01ff8304-05 csi dma buffer halfword 2 $01ff8306-07 csi dma buffer halfword 3 $01ff8306-07 csi dma buffer halfword 4 $01ff8306-07 csi dma buffer halfword 5 $01ff8306-07 csi dma buffer halfword 6 $01ff8306-07 csi dma buffer halfword 7 arm access to the csi buffers are provided for diagnostic purposes only and should not be used as part of normal operation. when the arm makes an access to these buffers, the arm is held off and clock domain synchronization occurs before the access is completed. as a result, a significant wait state penalty is incurred. this penalty will be even longer if a local dma operation is in progress when the access is made as the arm is held off for both the clock domain synchronization and the completion of the local dma transfer. there is a risk of data corruption when the arm makes write accesses to this buffer while a dma transfer is in progress. it is also possible that an access to this buffer can cause spurious writes to the scratchpad space while a dma transfer is in progress.
MFC2000 multifunctional peripheral controller 2000 hardware description 24-12 conexant 100723a 24.5 countach dma controller 24.5.1 function description this block handles data transfers between several of the blocks of the countach subsystem. it has three potential bus masters: the video/scan interface, the arm bus interface, and the countach subsystem. the vdma employs a hierarchical round-robin arbitration scheme, with the video/scan interface block at the highest priority and the countach subsystem and arm bus interface in a round-robin scheme at the lowest priority. a round-robin arbitration scheme is one in which no requestor can be serviced until all other requestors at the same priority have been serviced if they are also requesting. a hierarchical arbitration scheme is one in which if a higher priority group is requesting service it is given priority over a lower priority group, after which the lower priority group is handled in its predetermined manner. below is a table of the four dma channels, their functionality, and priorities. table 24-2. dma channels: functionality and priorities chan usage ++ ?? ?? ?? ?? 2d ? ? ? ? th ! ! ! ! priority description 0vsi """ a-1 scan/video data to (s)dram 1 csi i/o "" "" " b-1 countach scratch pad data to/from (s)dram 2abi in """ b-2 arm data to (s)dram 3 abi out """" b-3 arm data from (s)dram legend: chan dma channel vsi video/scanner interface csi countach subsystem interface abi arm bus interface ++ incrementing address ?? decrementing address 2d address jumping at boundaries. ? burst cycles th throttle: limits number of dma cycles per cbss clocks ! ! ! ! block limit notes: (1) to be supplied. channels 0,2, and 3 operate in a similar fashion as existing channels in the arm dma logic. these channels are programmed by arm-accessible registers and contain address registers and, for channel 3, a block limit and enable register. channel 1 is very different in its operation. it contains no arm-accessible registers. it is controlled by the countach subsystem. however, since the countach subsystem cannot be a bus master and program the registers directly, the countach dma logic must fetch the register values from the countach subsystem scratch pad. the countach subsystem has no dma handshaking signals as it is able to accept data at a fixed rate. dma data is transferred to and from the countach subsystem via the scratch pad at fixed addresses. thus, it appears as memory (sdram) to i/o (scratch pad) transfers. channel 1 is shared by five logical dma channels within the countach subsystem, but they operate consecutively, not concurrently (i.e., dma for one logical channel is completely before dma for another logical channel is begun. finally, logical dma channel 4 (of physical dma channel 1) is used for program dma. because
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-13 countach instructions are 40 bits wide, they must be transferred in sections. this is accomplished by dma transfers to three consecutive scratch pad addresses. each of the five logical channels is started by the countach subsystem by a high-going pulse on the countach gpio signal sp_gpio[0]. when the pulse is detected, the countach dma controller fetches the parameters from the scratch pad, executes the desired dma operation, and interrupts the countach subsystem at the completion. the scratch pad addresses for the various dma parameters are shown below: table 24-3. dma parameters scratch pad addresses scratch pad address parameter countach subsystem dma channel parameters 0xf9 enb ? enables the dma operation 0xfa bah ? most significant bits of base address and dma control bits 0xfb bal ? least significant bits of base address 0xfc sz ? number of halfwords to transfer 0xfd nsr ? number of sub ranges 0xfe ast ? address step between sub ranges scratch pad address function 0x100 countach subsystem dma channel 0 data port 0x101 countach subsystem dma channel 1 data port 0x102 countach subsystem dma channel 2 data port 0x103 countach subsystem dma channel 3 data port 0x1b0 countach subsystem dma channel 4 program data port (bits 15:0) 0x1b1 countach subsystem dma channel 4 program data port (bits 31:16) 0x1b2 countach subsystem dma channel 4 program data port (bits 39:32) to program and initiate a dma transfer, firmware must first setup the parameter registers shown above. the process of reading the enb register will cause hardware to generate either an arm irq or start a dma transfer. if the lsb of the enb register is 1 an arm irq is generated. if the value of the lsb is 0, a dma transfer is initiated. sub range value block size memory this diagram depicts how the sz, nsr and ast register all work together. the block size is controlled by the sz register and defines the number of dma accesses before the sub range jump occurs. at the end of the block, the last dma address + one is added to the ast register, and is used as the starting address for the next block. this process continues for the number of cycles specified by the nsr register. once the nsr value is met, an irq is generated.
MFC2000 multifunctional peripheral controller 2000 hardware description 24-14 conexant 100723a the meaning of the enb, bah, bal, sz, nsr, and ast parameters are shown below: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 not used program /data logical data channel number address direction data direction bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not used base address (21:16) parameter description : bah parameter bit 15-13 not used bit 12 when high, logical channel 4 is requested (program dma.) when low, one of logical channels 0-3 is requested as specified by the logical channel number field (data dma.) bit 11-10 logical data channel number when bit 12 is low, this field indicates which logical channel of 0-3 is to be used (data dma.) when bit 12 is high, this field is not used. bit 9 address direction when low, the dma address should be incremented after each halfword is transferred. when high, the dma address should be decremented after each halfword is transferred. bit 8 data direction when low, dma data is read from countach scratch pad space. when high, dma data is written to countach scratch pad space. bit 7-6 not used bit 5-0 upper bits of dma base address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 base address (15:8) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 base address (7:0) parameter description : bal parameter bit 15-8 lower bits of dma base address this parameter should only be fetched if the enable channel bit of the bah parameter is high. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 block size (15:8) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 block size (7:0) parameter description : sz parameter (refer to the above diagram)
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-15 bit 15 - 0 block size in halfwords block size = block size register + 1. if this parameter is zero, the channel should be considered improperly configured and not enabled. also, no further parameters need to be fetched in this circumstance. this register programs the data block size (number of dma accesses) between address steps, ast. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 number of sub ranges (15:8) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 number of sub ranges (7:0) parameter description: nsr parameter (refer to the above diagram) bit 15-0 number of sub ranges total number of sub ranges = register value + 1; when this register is set to $0000, one block will be transferred before the irq occurs. this register controls the number of number of sub ranges (nsr), or address steps that occur in the complete dma transfer. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address step between sub ranges (15:8) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address step between sub ranges (7:0) parameter description: ast parameter (refer to the above diagram) bit 15-0 address step between sub ranges this parameter should only be fetched if the enable channel bit of the bah parameter is high. this register controls the address step size between data blocks. the register value is added to the last dma address accessed in a block plus 1.
MFC2000 multifunctional peripheral controller 2000 hardware description 24-16 conexant 100723a 24.5.2 register description address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: video/scan high address one (vshiaddr1) $01ff828d (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: video/scan high address one (vshiaddr1) $01ff828c (not used) video /scan addr[22] video /scan addr[21] video /scan addr[20] video /scan addr[19] video /scan addr[18] video /scan addr[17] video /scan addr[16] rst value x0000000b read value 00h ? the value written to this register will not take effect until the lower address value is written. therefore this value should be set first. ? reading this register will return the address counter status, not the value written to this register. bit 15-7 not used bit 6-0 video/scan interface high address one [22:16] address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: video/scan low address one (vsloaddr1) $01ff828f video /scan addr[15] video /scan addr[14] video /scan addr[13] video /scan addr[12] video /scan addr[11] video /scan addr[10] video /scan addr[9] video /scan addr[8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: video/scan low address one (vsloaddr1) $01ff828e video /scan addr[7] video /scan addr[6] video /scan addr[5] video /scan addr[4] video /scan addr[3] video /scan addr[2] video /scan addr[1] (not used) rst value 0000000xb read value 00h ? writing to the video/scan low address register will load the address counter. therefore the upper address value should be set first. ? reading this register will return the address counter status, and not the value written to this register. bit 15-1 video/scan interface low address one [15:1] bit 0 not used
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-17 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: video/scan high address two (vshiaddr2) $01ff8291 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: video/scan high address two (vshiaddr2) $01ff8290 (not used) video /scan addr[22] video /scan addr[21] video /scan addr[20] video /scan addr[19] video /scan addr[18] video /scan addr[17] video /scan addr[16] rst value x0000000b read value 00h bit 15-7 not used bit 6-0 video/scan interface high address two [22:16] address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: video/scan low address two (vsloaddr2) $01ff8293 video /scan addr[15] video /scan addr[14] video /scan addr[13] video /scan addr[12] video /scan addr[11] video /scan addr[10] video /scan addr[9] video /scan addr[8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: video/scan low address two (vsloaddr2) $01ff8292 video /scan addr[7] video /scan addr[6] video /scan addr[5] video /scan addr[4] video /scan addr[3] video /scan addr[2] video /scan addr[1] (not used) rst value 0000000xb read value 00h address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: video/scan high address step (vshiaddrstep) $01ff8295 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: video/scan high address step (vshiaddrstep) $01ff8294 (not used) video /scan step [22] video /scan step [21] video /scan step [20] video /scan step [19] video /scan step [18] video /scan step [17] video /scan step [16] rst value x0000000b read value 00h bit 15-5 not used bit 6-0 video/scan interface high address step [22:16]
MFC2000 multifunctional peripheral controller 2000 hardware description 24-18 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: video/scan low address step (vsloaddrstep) $01ff8297 video /scan step[15] video /scan step[14] video /scan step [13] video /scan step [12] video /scan step [11] video /scan step [10] video /scan step [9] video /scan step [8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: video/scan low address step (vsloaddrstep) $01ff8296 video /scan step [7] video /scan step [6] video /scan step [5] video /scan step [4] video /scan step [3] video /scan step [2] video /scan step [1] (not used) rst value 0000000xb read value 00h bit 15-1 video/scan interface low address step [15:1] bit 0 not used address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: video/scan mode (vsmode) $01ff8299 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: video/scan mode (vsmode) $01ff8298 (not used) (not used) (not used) (not used) (not used) (not used) (not used) video /scan select rst value xxxxxxx0b read value 00h bit 15-1 not used bit 0 video/scan select a zero selects video capture mode and a one selects scan mode. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: arm bus a2c high address (aba2chiaddr) $01ff829d (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: arm bus a2c high address (aba2chiaddr) $01ff829c (not used) arm bus input addr[22] arm bus input addr[21] arm bus input addr[20] arm bus input addr[19] arm bus input addr[18] arm bus input addr[17] arm bus input addr[16] rst value x0000000b read value 00h bit 15-7 not used bit 6-0 arm bus interface input (a2c) data high address [22:16]
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-19 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: arm bus a2c low address (aba2cloaddr) $01ff829f arm bus input addr[15] arm bus input addr[14] arm bus input addr[13] arm bus input addr[12] arm bus input addr[11] arm bus input addr[10] arm bus input addr[9] arm bus input addr[8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: arm bus a2c low address (aba2cloaddr) $01ff829e arm bus input addr[7] arm bus input addr[6] arm bus input addr[5] arm bus input addr[4] arm bus input addr[3] arm bus input addr[2] arm bus input addr[1] (not used) rst value 0000000xb read value 00h bit 15-1 arm bus interface input (a2c) data low address [15:1]. bit 0 not used address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: arm bus c2a high address (abc2ahiaddr) $01ff82a1 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: arm bus c2a high address (abc2ahiaddr) $01ff82a0 (not used) arm bus output addr[22] arm bus output addr[21] arm bus output addr[20] arm bus output addr[19] arm bus output addr[18] arm bus output addr[17] arm bus output addr[16] rst value x0000000b read value 00h bit 15-7 not used bit 6-0 arm bus interface output (c2a) data high address [22:16] address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: arm bus c2a low address (abc2aloaddr) $01ff82a3 arm bus output addr[15] arm bus output addr[14] arm bus output addr[13] arm bus output addr[12] arm bus output addr[11] arm bus output addr[10] arm bus output addr[9] arm bus output addr[8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: arm bus c2a low address (abc2aloaddr) $01ff82a2 arm bus output addr[7] arm bus output addr[6] arm bus output addr[5] arm bus output addr[4] arm bus output addr[3] arm bus output addr[2] arm bus output addr[1] (not used) rst value 0000000xb read value 00h bit 15-1 arm bus interface output (c2a) data low address [15:1] bit 0 not used
MFC2000 multifunctional peripheral controller 2000 hardware description 24-20 conexant 100723a address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: arm bus c2a block size (abc2ablksiz) $01ff829b arm bus output enable arm bus output block size [14] arm bus output block size [13] arm bus output block size [12] arm bus output block size [11] arm bus output block size [10] arm bus output block size [9] arm bus output block size [8] rst. value 00h read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: arm bus c2a block size (abc2ablksiz) $01ff829a arm bus output block size [7] arm bus output block size [6] arm bus output block size [5] arm bus output block size [4] arm bus output block size [3] arm bus output block size [2] arm bus output block size [1] arm bus output block size [0] rst. value 00h read value 00h bit 15 arm bus interface output (c2a) data dma enable (1 = enabled) bit 14-0 arm bus interface output data block size note : writes to bits 14-0 are ignored when the channel is enabled. to write a new block size, the channel must first be disabled by writing a ?0? to bit 15 of this register. address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: arm bus a2c throttle (aba2cthrottle) $01ff82a5 (not used) (not used) (not used) (not used) (not used) arm bus input throttle[10] arm bus input throttle[9] arm bus input throttle[8] rst. value xxxxx000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: arm bus a2c throttle (aba2cthrottle) $01ff82a4 arm bus input throttle[7] arm bus input throttle[6] arm bus input throttle[5] arm bus input throttle[4] arm bus input throttle[3] arm bus input throttle[2] arm bus input throttle[1] arm bus input throttle[0] rst value 00h read value 00h bit 15-11 not used bit 10-0 arm bus interface input (a2c) dma throttle value a value of zero indicates no throttle. a value of 3ffh indicates 2047 countach bus subsystem clocks (25 mhz) between successive dma acknowledges.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-21 address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: arm bus c2a throttle (abc2athrottle) $01ff82a7 (not used) (not used) (not used) (not used) (not used) arm bus output throttle[10] arm bus output throttle[9] arm bus output throttle[8] rst. value xxxxx000b read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: arm bus c2a throttle (abc2athrottle) $01ff82a6 arm bus output throttle[7] arm bus output throttle[6] arm bus output throttle[5] arm bus output throttle[4] arm bus output throttle[3] arm bus output throttle[2] arm bus output throttle[1] arm bus output throttle[0] rst value 00h read value 00h bit 15-11 not used bit 10-0 arm bus interface output (c2a) dma throttle value a value of zero indicates no throttle. a value of 3ffh indicates 2047 countach bus subsystem clocks (25 mhz) between successive dma acknowledges. 24.5.3 firmware operation cdma channel 0 setup and operation 1. program the dma controller ? select mode ? for video mode set up address register 2 ? write jump value ? write address register 1. this will also initialize the channel by setting up the address holder and address counter. 2. operation ? at the end of each line of data the vsi_eol will pulse, causing the holder value to be added to the jump value and placed back into the address holder. ? for video mode, multiple vsi_eols will occur, then a vsi_eof. upon the 1 st vsi_eof, the address register2 will be loaded into the holder and counter. ? additional vsi_eols will occur and then a 2 nd vsi_eof. upon the 2 st vsi_eof the irq will be asserted.
MFC2000 multifunctional peripheral controller 2000 hardware description 24-22 conexant 100723a 24.6 video/scanner interface 24.6.1 function description the video/scan interface connects the video/scan controller to the sdram via dma cycles. this interface has a unidirectional data flow: video/scan controller to sdram. it consists of two 64 halfword buffers that ping-pong, address counters for video/scan controller input, and cdram output and byte to halfword assembly. the video/scan controller transmits a single line when attached to the scanner input or a single frame when attached to the video input. in either case, the video/scan controller data flow is as follows: 1. the video/scan controller initiates a transfer by a single high-going pulse on the start signal to vsi . 2. as each analog sample becomes available, it is placed on the vsc output bus and the data ready signal is pulsed high to vsi. in the case of video capture, it is expected that the data ready signal will remain high for long periods of time as video data is available at each rising edge of the data clock. in the case of scanner capture, it is expected that the data ready signal will be inactive for several data clocks between successive pixels. 3. as the video/scan interface receives data from the video/scan controller, it is assembled into halfwords and then stored into one of the two ping-pong buffers. when the buffer is filled, data storing is switched to the remaining buffer and a signal is passed to the opposite side of the interface indicating a buffer is available for transfer. 4. the video/scan controller terminates the transfer by a single high-going pulse on the stop signal. 5. on the countach bus subsystem side of the video/scan interface, the data flow is as follows: 6. a pulse is received from the video/scan controller side of the video/scan interface indicating a buffer is available for transfer. 7. vsi asserts the dma request signal to cbu. the sequencial dma signal is also asserted if the buffer contains more than one halfword of data. 8. once the dma acknowledge signal is detected, transfer begins, one data being transferred for each sdram ready pulse. 24.6.2 register description address: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default: video/scanner interface mode (vsimode) $01ff8289 (not used) (not used) (not used) (not used) (not used) (not used) (not used) (not used) rst. value xxh read value 00h address: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default: video/scanner interface mode (vsimode) $01ff8288 (not used) (not used) (not used) (not used) (not used) (not used) video/scanner dma hog mode[1] video/scanner dma hog mode[0] rst value xxxxxx00b read value 00h bit 15-2 not used bit 1-0 the video/scanner dma hog mode field is used to throttle and/or disable other dma masters during video capture. it has the following settings: hog mode countach subsystem interface arm bus interface 0 burst and single dma allowed burst and single dma allowed 1 no burst ? single dma only no burst ? single dma only 2 no dma allowed no burst ? single dma only 3 no dma allowed no dma allowed
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-23 24.6.3 internal memory the video/scanner interface contains two 64x16 buffers for dma transfers from the video/scanner controller and the countach sdram. the buffers can be accessed by the arm as halfwords only. the two buffers are located at the following address: ping pong buffer 1: $01ffa400 ? $01ffa47f ping pong buffer 2: $01ffa480 ? $01ffa4ff arm access to the vsi buffers is provided for diagnostic purposes only and should not be used as part of normal operation. when the arm makes an access to the buffers, the arm is held off and clock domain synchronization occurs before the access is completed. as a result, a significant wait state penalty is incurred. 24.7 (s)dram controller ((s)dramc) 24.7.1 function description the (s)dram controller is used to communicate between the countach bus unit (cbu) and external fpdram or sdram memory. this memory will primarily be used for reading and writing large amounts of sequential data necessary for carrying out the programs running on the countach imaging dsp core. whether dram or sdram is used is an option, but only one memory unit is accessible to the memory controller. the (s)dramc state machine uses a 100mhz or 87.5mhz clock to control the sdram and dram. the cbu will communicate with (s)dramc at 25 mhz or 21.875mhz, so all data received from either ram type must be synchronized to this speed before sent to the cbu. a third clock, an inverted version of the 100mhz or 87.5mhz clock, will be sent to the sdram memory. in this document, 100mhz clock will be used for all descriptions. from the timing point of view, 87.5mhz will be covered if it meets 100mhz requirements. the supported dram characteristics are listed in the following table: table 24-4: supported fpdram chip characteristics addressing size: 2 mb, 8 mb organization: 16 bits access speed: 50 ns, 60 ns table 24-5: supported sdram chip characteristics addressing size: 2 mb, 8 mb organization: 8 bits or 16 bits access speed: 10 ns the maximum memory size that is supported for either memory type is 8mb. six possible row/column pinouts types are supported. a more detailed description can be found in the address multiplexing table. sdram will always be used in burst mode, with one access per burst. the cas latency will be set to 3 cycles which is normal for sdram running at 100mhz. the two possible sizes and two possible organizations are programmable in the (s)dramc control register. fast page mode drams (50ns and 60ns) are supported. the speed requirement is due to the bandwidth requirements of the countach imaging dsp. the drams will be used in both fast page burst mode and single access mode. the two possible densities which are supported are programmable in the (s)dramc control register.
MFC2000 multifunctional peripheral controller 2000 hardware description 24-24 conexant 100723a 24.7.1.1 memory bank structure there will only be one bank of memory allowed. accesses to those banks must be done as halfword (16 bit) accesses. sdram with 8-bit data bus will not be byte addressable as far as the system in concerned. instead, each 16-bit access will write or read two consecutive bytes of data to/from the 8-bit sdram. for instance, a request to access to byte location 0x100 or 0x101 in 8-bit sdram will both access the same halfword (16-bit) location. hardware does not support byte access to external memory connected to (s)dram. 24.7.1.2 wait state profile 50 ns fpdram read requests will have two 25mhz wait states for the first read access and zero wait states for each successive read. so the fpdram read wait state profile is considered to be 2-0-0-0. for example, a burst of four reads will take six cycles to complete; three for the first read, and three total for the next three reads. for 60ns fpdram, the read wait state profile is 2-0-1-0-1-0, etc. the write wait state profile for 50ns fpdram is 1-0-0-0. the write wait state profile for 60 ns fpdram is 1-0-1-0-, etc. sdrams will have an identical wait state profile regardless of whether they use a 16 bit data bus or 8 bit data bus. writes will have a profile of 1-0-0-0. reads will have a wait state profile of 2-0-0-0. in either case when the burst or single access is finished, there will be a 1 cycle penalty in order to satisfy trc. 24.7.1.3 address multiplexing when reading chart, note that the address bits and data bit on the leftmost column correspond to the actual bits which are output of the (s)dramc block (also outputs of asic), whereas the address bits in the row/col columns correspond to the input addresses to the (s)dramc block (which are aligned to halfword boundary). in other words, the address requested by cbu will be a halfword address, not a byte address. as a result, the cbu and (s)dramc will communicate via a 22-bit address bus. in the following charts, ma[x] refers to the memory address pin located on the MFC2000 asic (i.e.,. cdao[x]). md[x] refers to the memory data pin located on the MFC2000 asic (i.e.,cddo[x]). ba[x] refers to the bank pin on the sdram part. ea[x] refers to the external address pin located on the ram part. so the external address column of the chart shows the actual connection between the MFC2000 and the ram. (i.e., looking at the first row of the chart, there will be a wire connecting ma[12] of the MFC2000 to the ba1 of the sdram). a[x], within the row/col columns of the chart, refers to the 22-bit address bus within the chip
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-25 table 24-6. untitled table address multiplexing register sdram 64 mb (16 bit data bus) (14 x 8) sdram 64 mb (8-bit data bus) (14 x 9) sdram 16 mb (16 bit data bus) (12 x 8) sdram 16 mb (8 bit data bus) (12 x 9) external address row col. row col. row col. row col. ma[12]/ba[1] a[21] a[21] a[21] a[21] 0 0 0 0 ma[11]/ba[0] a[20] a[20] a[20] a[20] 0 0 0 0 ma[10]/ea[11] a[19] 0 a[19] 0 a[19] a[19] a[19] a[19] ma[9]/ea[10] a[18] 0 1 a[18] 0 1 a[18] 0 1 a[18] 0 1 md[0]/ea[9] a[17] nc 3 a[17] nc 3 a[17] nc 3 a[17] nc 3 ma[8]/ea[8] a[16] 0 a[16] (0 or 1) 2 a[16] 0 a[16] (0 or 1) 2 ma[7]/ea[7] a[15] a[7] a[15] a[7] a[15] a[7] a[15] a[7] ma[6]/ea[6] a[14] a[6] a[14] a[6] a[14] a[6] a[14] a[6] ma[5]/ea[5] a[13] a[5] a[13] a[5] a[13] a[5] a[13] a[5] ma[4]/ea[4] a[12] a[4] a[12] a[4] a[12] a[4] a[12] a[4] ma[3]/ea[3] a[11] a[3] a[11] a[3] a[11] a[3] a[11] a[3] ma[2]/ea[2] a[10] a[2] a[10] a[2] a[10] a[2] a[10] a[2] ma[1]/ea[1] a[9] a[1] a[9] a[1] a[9] a[1] a[9] a[1] ma[0]/ea[0] a[8] a[0] a[8] a[0] a[8] a[0] a[8] a[0] 1. ea[10] is used on sdrams for auto-precharge during column access. auto-precharge will not be utilized by cdram so ea[10] will always be set to 0 during column access. 2. ea[8] will be used as the byte control bit for 8-bit sdrams. addresses sent to cdram from the cbu will always be halfword addressable. in order to communicate with 8-bit sdrams, cdram toggles ea[8] and obtains two sequential pieces of 8-bit data and sends it back to the system as one 16-bit data chunk. 3. since md[0] is used both as a data pin and an address pin, during the column portion of a sdram access, the sdram will not read from the ea[9] pin. so ea[9] is no-care [nc] during this time. although at that time, md[0] may very well be carrying valid data to the data bus.
MFC2000 multifunctional peripheral controller 2000 hardware description 24-26 conexant 100723a table 24-7. untitled table address multiplexing register dram 16 or 64 mb (16 bit data bus) 12 x 10 or 10 x 10 1 dram 16 mb (16 bit data bus) 12 x 8 physical address row col. row col. ma[12]/ea[11] a[21] 0 a[19] 0 ma[11]/ea[10] a[20] 0 a[18] 0 ma[10]/ea[9] a[19] a[9] a[17] 0 ma[8]/ea[8] a[18] a[8] a[16] 0 ma[7]/ea[7] a[17] a[7] a[15] a[7] ma[6]/ea[6] a[16] a[6] a[14] a[6] ma[5]/ea[5] a[15] a[5] a[13] a[5] ma[4]/ea[4] a[14] a[4] a[12] a[4] ma[3]/ea[3] a[13] a[3] a[11] a[3] ma[2]/ea[2] a[12] a[2] a[10] a[2] ma[1]/ea[1] a[11] a[1] a[9] a[1] ma[0]/ea[0] a[10] a[0] a[8] a[0] 1. in the 10x10 version, ma[11] and ma[12] will be left unconnected table 24-8. untitled table memory size/type supported/not supported row/column configuration row column 512k x 16 x 2 bank sdram (16 mb) supported 11 2 banks (1 bit) 8 1m x 8 x 2 bank sdram (16 mb) supported 11 2 banks (1 bit) 9 1m x 16 x 4 bank sdram (64 mb) supported 12 4 banks (2 bits) 8 2m x 8 x 4 bank sdram (64 mb) supported 12 4 banks (2 bits) 9 2m x 16 x 2 bank sdram (64 mb) supported 13 2 banks (1 bit) 8 4m x 8 x 2 bank sdram (64 mb) supported 13 2 banks (1 bit) 9 1m x 16 dram supported 12 8 (16 mb) supported 10 10 4m x 16 dram supported 12 10 (64 mb) not supported 13 9
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-27 as seen in the preceding tables, special care must be taken when connecting a fpdram or sdram to the MFC2000 for use with (s)dramc. in summary, when using fpdrams, a[8:0] of the dram should be connected to ma[8:0] of the (s)dramc. a[11:9] of the dram should be connected to ma[12:10] of the (s)dramc. when using sdrams, for 64 mb type, a[8:0] of the sdram should be connected to ma[8:0] of the (s)dramc. a[9] of the sdram should be connected to md0 of the (s)dramc. a[13:10] of the sdram should be connected to ma[12:9] of the (s)dramc. consequently, the md0 pin out of the (s)dramc is time multiplexed with address information during the row address portion of a sdram access and contains data information during the column address portion of a sdram access. this was done to conserve pin usage of the MFC2000. for the same reason, any dqm pins of an sdram should be connected to ground. the cke pin of the sdram should be connected high. also, if two bank 64mb sdram is being used (the chart describes four bank), ma[11] should be connected to ea[12] since there will only be one bank pin (as compared to the four bank sdram in which there are two bank pins). for board layout: in order to maintain low delay and minimized crosstalk, the sdram should be placed no farther than 0.5 inch from the MFC2000.
MFC2000 multifunctional peripheral controller 2000 hardware description 24-28 conexant 100723a 24.8 register description name/address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default dram configuration 0x01ff8281 na na na na na na na na rst. value ?h00 read value ?h00 name/address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default dram configuration 0x01ff8280 na na na cdram clock enable configuration code rst. value ?h00 read value ?h00 this register contains the information necessary to decide whether dram or sdram is being used, the size of memory being used, and whether an 8- or 16-bit dram is being used. this register should be written to once and only once as the cdram may not work properly if this is written to a second or more times. in addition, most rams require a minimum of 100us delay before use in order for the ram to stabilize, but some others require more time. to properly use the ram, this register should be written to only after the appropriate delay for that particular ram is met. writing to this register will cause the cdram to perform the proper ammount of refreshes, the precharge, and mode set necessary for correct startup of dram or sdram. bit 15-5 bit 4 cdram clock enable this bit enables or disables the cdram external clock. when using fpdram, the clock does not need to be enabled. 0: enable 1: disable bit 3-0 dram type configuration code sdram 8-bit 16 mb 0010 sdram 8-bit 64 mb 0110 sdram 16-bit 16 mb 0000 sdram 16-bit 64 mb 0100 fpdram 60ns 16 mb (10x10) 0111 fpdram 60ns 16 mb (12x8) 0011 fpdram 60ns 64 mb (12x10) 0111 fpdram 50ns 16 mb (10x10) 1111 fpdram 50ns 16 mb (12x8) 1011 fpdram 50ns 64 mb (12x10) 1111
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-29 24.8.1 timing 24.8.1.1 detailed timing measurements sdrasn, sdcasn, sdcsn, sdrwn sdaddr t cms t as sddata t ds sdclk100 t cmh t ah t dh figure 24-2. sdram setup and hold timing table 24-9. sdram setup and hold timing parameter symbol min. max. units command setup time (includes rasn, casn, wen, csn) t cms 4ns command hold time t cmh 3ns address setup time t as 4ns address hold time t ah 3ns data setup time t ds 4ns data hold time t dh 3ns
MFC2000 multifunctional peripheral controller 2000 hardware description 24-30 conexant 100723a addr sdclk100 command act rd/wr rd/wr rd/wr pre act row address column address column address column address bank r c c c row address trcd tdpl trp trc figure 24-3. sdram read or write timing command sdaddr sdclk100 pre mode ref trp trsc figure 24-4. sdram mode timing note : in the above sdram timing waveforms ?command? is a combination of rasn, casn, wen, and csn. sdcasn sdrasn sdaddr sddata sdcsn sdwrn refresh row active sdclk100 trc figure 24-5. sdram refresh timing
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-31 table 24-10. timing parameters for 16-bit sdram read and write parameter symbol min. max. units clock period t clk 10 ns ras precharge time t rp 3 (5 for single access) t clk mode register set to active delay t rsc 4t clk ras cycle time t rc 12 t clk ras-to-cas delay t rcd 3t clk data-in to pre command period t dpl 2 (4 for single access) t clk table 24-11. timing parameters for 8-bit sdram read and write parameter symbol min. max. units clock period t clk 10 ns ras precharge time t rp 5 (5 for single access) t clk mode register set to active delay t rsc 4 t clk ras cycle time t rc 12 t clk ras-to-cas delay t rcd 3 t clk data-in to pre command period t dpl 3 (3 for single access) t clk d1 d2 d3 d4 row col1 col2 col3 col4 sdcasn sdrasn sdwrn (write cycle) sdaddr[12:0] sddata[15:0] (write cycle) trcd trah tras trp trc tcas tcah tcp tpc tds tdh tasr tasc figure 24-6. fpdram timing (read or write)
MFC2000 multifunctional peripheral controller 2000 hardware description 24-32 conexant 100723a table 24-12. 60ns timing parameter symbol min. max. units ras pulse width t ras 70 ns cas pulse width t cas 20(30 for read) ns ras-to-cas delay t rcd 40 ns ras precharge t rp 50 ns cas precharge t cp 40 ns column address setup t asc 10 ns column address hold t cah 30 ns row address setup t asr 10 ns row address hold t rah 20 ns fast page mode cycle t pc 60 ns ras-to-ras delay t rc 120 ns data setup time t ds 20 ns data hold time t dh 30 ns table 24-13. 50ns timing parameter symbol min. max. units ras pulse width t ras 70 ns cas pulse width t cas 20(30 for read) ns ras-to-cas delay t rcd 30 ns ras precharge t rp 50 ns cas precharge t cp 20(10 for read) ns column address setup t asc 10 ns column address hold t cah 20(30 for read) ns row address setup t asr 10 ns row address hold t rah 20 ns fast page mode cycle t pc 40 ns ras-to-ras delay t rc 120 ns data setup time t ds 20 ns data hold time t dh 30 ns note : the most notable difference between the 50ns and 60ns timing is the tpc parameter. during bursts, 50ns is able to perform much faster.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-33 t crd t rcas sdclk100 sdrasn sdcasn sdwrn t rras figure 24-7. fpdram timing (refresh) table 24-14. fpdram timing (refresh) parameter symbol min. max. units oe delay t oed 6 ns casn pulse width t rcas 28 ns rasn pulse width t rras 60 ns casn to rasn delay t crd 9 ns
MFC2000 multifunctional peripheral controller 2000 hardware description 24-34 conexant 100723a 24.8.2 firmware operation there is only one operation in which firmware need be concerned with the cdram block. that operation is the powerup operation. during startup, dram and sdram both have a specific sequence which needs to be performed on them in order for them to function properly. in order to assure that this sequence is properly performed the following must be done: 1. wait a minumum of 200us. some memories require as little as 100us, while a few others require as great as 500us. waiting 200us will assure that most memories will work correctly. 2. write to the cdram configuration register. this register should be written to once and only once. unless this register is written to, cdram will not know what type of ram is being used. 3. that?s it. after about a 1 us delay the startup procedure should be finished and the memory ready to be accessed. an access request can be made after the startup procedure is done and before it is finished, but the access will not occur until the complete startup procedure is finished.
hardware description mfc 2000 multifunctional peripheral controller 2000 100723a conexant 24-35 this page is intentionally blank

multifunctional peripheral controller 2000 MFC2000 100723a conexant 25-1 25. configuration 25.1 hardware version address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default hardware version (hwver) $01ff8045 (r) (not used) rst. value xxh read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default hardware version (hwver) $01ff8044 (r) 0:= first release 1-ff:= other releases rst. value 00h read value 00h this register is used to content the hardware version number. the value in this register is 0 for first release of a product. whenever the hardware design is modified, this register value is incremented. this register is not effected by any reset. 00h ? MFC2000_x1 (the pqfp package) 25.2 product code address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default product code (productcode) $01ff8047 (r) (not used) rst. value xxh read value 00h address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default product code (productcode) $01ff8046 (r) product code: bfh: 11626-11, with data modem function, with voice codec/speaker phone function, and with smartdaa support bdh: 11626-12, with data modem function, without voice codec/speaker phone function, and with smartdaa support bbh: 11626-13, without data modem function, with voice codec/speaker phone function, and with smartdaa support b9h: 11626-14, without data modem function, without voice codec/speaker phone function, and with smartdaa support b8h: 11626-15, without data modem function, without voice codec/speaker phone function, and without smartdaa support rst. value (must match with the product code) this register is not affected by any reset.
MFC2000 multifunctional peripheral controller 2000 hardware description 25-2 conexant 100723a this page is intentionally blank
multifunctional peripheral controller 2000 MFC2000 doc. no. 100723a conexant inside back cover notes
further information literature@conexant.com (800) 854-8099 (north america) (949) 483-6996 (international) printed in usa world headquarters conexant systems, inc. 4311 jamboree road newport beach, ca 92660-3007 phone: (949) 483-4600 fax 1 : (949) 483-4078 fax 2 : (949) 483-4391 americas u.s. northwest/ pacific northwest ? santa clara phone: (408) 249-9696 fax: (408) 249-7113 u.s. southwest ? los angeles phone: (805) 376-0559 fax: (805) 376-8180 u.s. southwest ? orange county phone: (949) 483-9119 fax: (949) 483-9090 u.s. southwest ? san diego phone: (858) 713-3374 fax: (858) 713-4001 u.s. north central ? illinois phone: (630) 773-3454 fax: (630) 773-3907 u.s. south central ? texas phone: (972) 733-0723 fax: (972) 407-0639 u.s. northeast ? massachusetts phone: (978) 367-3200 fax: (978) 256-6868 u.s. southeast ? north carolina phone: (919) 858-9110 fax: (919) 858-8669 u.s. southeast ? florida/ south america phone: (727) 799-8406 fax: (727) 799-8306 u.s. mid-atlantic ? pennsylvania phone: (215) 244-6784 fax: (215) 244-9292 canada ? ontario phone: (613) 271-2358 fax: (613) 271-2359 europe europe central ? germany phone: +49 89 829-1320 fax: +49 89 834-2734 europe north ? england phone: +44 1344 486444 fax: +44 1344 486555 europe ? israel/greece phone: +972 9 9524000 fax: +972 9 9573732 europe south ? france phone: +33 1 41 44 36 51 fax: +33141443690 europe mediterranean ? italy phone: +39 02 93179911 fax: +39 02 93179913 europe ? sweden phone: +46 (0) 8 5091 4319 fax: +46 (0) 8 590 041 10 europe ? finland phone: +358 (0) 9 85 666 435 fax: +358 (0) 9 85 666 220 asia ? pacific taiwan phone: (886-2) 2-720-0282 fax: (886-2) 2-757-6760 australia phone: (61-2) 9869 4088 fax: (61-2) 9869 4077 china?central phone: 86-21-6361-2515 fax: 86-21-6361-2516 china?south phone: (852) 2 827-0181 fax: (852) 2 827-6488 china ? south (satellite) p hone: ( 86) 755 - 518 - 2495 china?north phone: (86-10) 8529-9777 fax: (86-10) 8529-9778 india phone: (91-11) 692-4789 fax: (91-11) 692-4712 korea phone: (82-2) 565-2880 fax: (82-2) 565-1440 korea (satellite) phone: (82-53) 745-2880 fax: (82-53) 745-1440 singapore phone: (65) 737 7355 fax: (65) 737 9077 japan phone: (81-3) 5371 1520 fax: (81-3) 5371 1501 www.conexant.com 0 . 0 sa l es offi ces


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